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It's funny.
A person who designs such a complex project must know how to describe a set of
128 registers.
Another hand, this register memory is rather complex and may afford
some invention efforts because the register content takes part both in
ALU operations and as address index and in bit handling operations.
Anyway, they can be inferred from a clocked process like
Process(clk,rst)
if rst='1' then
reg(18)<=X"00"; -- stack pointer
elsif clk='1' and clk'event then
if rg_ena='1' then
case(addrwr) is
when X"00" => reg(0)<=DI;
...
when X"7f"=>reg(127)<=DI;
...
end case;
end if;
end if;
end process;
DO1<=reg(conv_integer(addrrd1));
DO2<=reg(conv_integer(addrrd2));
...
or something like this.
A BlockRAM can be instantiated, but the registers must be treated in sequence.
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