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VHDL Query - entity port as int array, not std_logic_vector

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santom

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VHDL Query

HI,
I would like to ask people here whether I can declare an entity port parameter say 'result' as an integer array instead of conventional std_logic_vector array.

I want to store some integer numbers and also few character symbols in that 'result' array.But I am not able to proceed further as I am getting stuck with this problem here.

I am in a plan to pass this 'result' array to the next program as an input.Can anyone here guide me as how to go about it.

Santom
 

VHDL Query

How about creating a record and put individual parameters in the members of that record, it is easier to manage and for synthesis it works without any problems.
The only problem with this aproach is that you end up with a HUGE design if you decide to actually syntheisze it.
 

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