DAC noise simulations in Cadence

dac noise

Hi, I have designed a current mode 8bit DAC with an output range of 0uA-8uA (can be changed) in 90nm CMOS. The goal is low speed/power consumption. However I am not sure if the DAC actually can be fabricated and work properly.

I have some questions regarding verification, especially noise simulations.

I did a transient noise simulation in Cadence with the following parameters:

noiseseed: 1
noisefmax: 5G
noisescale: 1

The simulation showed ALOT of noise, enough to render the DAC ENOB equal to 3bit instead of 8bit.

Is this a realistic noise simulation for the DAC?

By the way, normal transient simulation (transient noise excluded) shows good response in terms of DNL, INL and low glitching. Including Monte Carlo simulations.

If anyone has any idea about a good way of simulating DAC noise so that one can get an good estimation on how the DAC will perform post fabrication, any tips on this topic are greatly appreciated. Perhaps a checklist of simulations I should perform?

(PS I do not have any experience with noise simulations in Cadence)

dac noise model

I would be concerned about getting the transient noise
amplitude "calibrated", the canonical noise params
which a foundry PDK might model, are not really the
same thing when you try transient noise (I gather
from some very superficial reading).

I think you should get a "standard transistor" (by the
foundry's noise modeling documentation) and try a
static, transient noise simulation and process the
output noise amplitude / spectrum back to a
nV/sqrtHz (or whatever) number, maybe compare
curves if they are shown in PDK docs, to the point
that you believe the fundamental "input" is right.

I think there is a good chance that tnoise params may
not have been set, or set to defaults, and you are hit
with the result.

The transient noise simulation in cadence has a bug and does not work when you have a switch in series with a current source because the noise update is not done when the switch turns on and off but rather every 1/(noise bandwidth segment).
In the newer versions of mmsim this has been fixed.

Tnx for the replies!

I do not have access to the PDK documentation at the moment so I cant compare the noise results of a standard transistor. Its hard to get ones hands on the documentation because universities are considered to be to "public" for such material to be easily available.

I did a simulation on a standard PMOS current mirror and a current mirror with active feedback. I also added a PMOS switch in series and got the results displayed in the attachment. The mirrored current is 500nA where the upper curve is from the current mirror with active feedback and the curve below it is a standart current mirror. All transistors are dimensioned W/L=10um/2um.

Does this look realistic? Or should I not worry to much about this simulation?