konradb
Newbie level 6
vhdl logic_vector
I wish to take a 16-bit logic vector in (from an ADC). This is an AC-biased sine wave connected to an ADC centered around the mid point of the ADC (i.e. 32767).
How do I change this to a signed integer that i then use to do a multiply and subsequently output as a signed logic vector?
I have some code snipets below,
------------------
Library IEEE;
Use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_signed.all;
DAT_I : in std_logic_vector(15 downto 0);
DAT_O : out std_logic_vector(15 downto 0);
signal A_int: integer range -2147483647 to 2147483647;
signal result_int: integer range -2147483647 to 2147483647;
A_int <= conv_integer(DAT_I);
Result_int <= (A_int-32767) * coef_int; -- convert A to signed 16-bit and multiply
DAT_O(15 downto 0) <= conv_std_logic_vector(result_int,16);
------------------
does the above give me a signed DAT_O?
Do I need to replace the following?
A_int <= conv_integer(unsigned(DAT_I));
I wish to take a 16-bit logic vector in (from an ADC). This is an AC-biased sine wave connected to an ADC centered around the mid point of the ADC (i.e. 32767).
How do I change this to a signed integer that i then use to do a multiply and subsequently output as a signed logic vector?
I have some code snipets below,
------------------
Library IEEE;
Use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_signed.all;
DAT_I : in std_logic_vector(15 downto 0);
DAT_O : out std_logic_vector(15 downto 0);
signal A_int: integer range -2147483647 to 2147483647;
signal result_int: integer range -2147483647 to 2147483647;
A_int <= conv_integer(DAT_I);
Result_int <= (A_int-32767) * coef_int; -- convert A to signed 16-bit and multiply
DAT_O(15 downto 0) <= conv_std_logic_vector(result_int,16);
------------------
does the above give me a signed DAT_O?
Do I need to replace the following?
A_int <= conv_integer(unsigned(DAT_I));