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LNA circuit in RFIC- LNA's gain is lower than simulated

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fly_fish

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LNA 's gain

I have designed a LNA circuit in RFIC with charted RF CMOS 0.18um process.
The LNA's measured current and bias voltage agree with its simulated ones.
Also, the LNA's input and output port have been matched well with VSWR<2 at 1.55GHz.
However, the LNA's gain at 1.55GHz is only 5dB, far lower than the simulated vaule-15dB.
Anyone can tell me why? Thanks!
 

LNA 's gain

maybe you can check the parasite effect of the layout.What is your gain result obtained by post layout simulation?
 

LNA 's gain

how you setup the measurement ?
Is it possible the LNA is loaded by noise measurement equipment?
 

LNA 's gain

The gain result obtained from post layout simulation is 15dB.
hello, fanshuo, your " is invalid. So I can't understand your reply.
The LNA's input port is connected to Agilent's signal source , and its ouput port is connected to spectrum analyzer.
 

Re: LNA 's gain

Added after 1 minutes:

Hi,

At such a high frequency your parasitics will be very critical (Bond wire parasitics, Package parasitics, board parasitics) include these parasitics into your layout and resimulate it, definitly you will see the difference.

Check for your device source to ground inductance which is an imporatant killing factor to reduce your gain and I am very sure please check for it. It should be very short and wide enough, so that the inductance will be less

Let me know if this will help......

dipak................
 

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