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shiva_107

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You have two clocks, CLK1, CLK2 goes as inputs to a MUX, you have a select line. The output of this mux goes to the clk of flip flop.
What additional circuit you should add such that if you switch from one clock to another you should not see any glitches.
____ ____
CLK1 - ___| |____| |____
____ ____
CLK2- _| |___| |____
_________________
sel - ____|


sel 0 selects clk1, sel 1 selects clk2...in this case you will see a glitch.
 

from the picture that you drew, it looks like the clocks are not 50% duty cycle. In that case, we can build a circuit to avoid glitches if we ONLY change the select value when both clocks are low.



The Select value is buffered, and overpowers a small cross-coupled inverter structure when both clocks are 0.
 

the only thing you need to do is make sure the mux switches when both clocks are low then you are gauranteed not to have any glitches.
 

shiva_107 said:
You have two clocks, CLK1, CLK2 goes as inputs to a MUX, you have a select line. The output of this mux goes to the clk of flip flop.
What additional circuit you should add such that if you switch from one clock to another you should not see any glitches.
____ ____
CLK1 - ___| |____| |____
____ ____
CLK2- _| |___| |____
_________________
sel - ____|


sel 0 selects clk1, sel 1 selects clk2...in this case you will see a glitch.
Click to expand...

Yes you will see glitch. e.g.
**broken link removed**


Suppose you have to change clock input run time, then you need to design noglitch mux. e.g.
**broken link removed**

HTH
--
Shitansh Vaghela
 

Interesting question.

ljxpjpjljx said:
further more, does it have limitation?
Click to expand...

What kinda limitation are you referring to?
 

u sure what glitch free mux is shown in link you pasted below will not give give any set-up violations? the ckt what u have shown is without any synchronizer .. and so it will have setup violation problems, is it not?

arjun1110 said:
Hi Shiva,

Go through is below link.

**broken link removed**

Regards
Click to expand...

Added after 1 minutes:

any conclusion on this question? this is really interesting and very practical question looks like ...
 

jaydip said:
u sure what glitch free mux is shown in link you pasted below will not give give any set-up violations?
Click to expand...

Hi

I had did long before exactly same application and i did not face any problem with that.

I have implemented this logic in Actel environment and you can refer
Contct saving application for Flash. which uses No Glitch mux

The Actel tool have NGMUX (noglitch mux), which is technology dependent. SeeUse of NGMUX in Actel tool

But you can download similar code of No Glitch mux from link i shown in ablove reply.

Also you can refer

jaydip said:
the ckt what u have shown is without any synchronizer .. and so it will have setup violation problems, is it not?
Click to expand...

Suppose you are thinking to synchronize output clock, then with which reference clock you will synchronize output clock?!!!!!

Basically synchronizer used when any signal enters in one clock domain form another clock domain, but here the application is switching of clock so synchronizer
not needed.

Let others give more light on this.



HTH,
--
Shitansh Vaghela
 

hi,

Here is another techniq for glitch free clock switching, this time i used this one and worked properly.

Source code and reference document are attached.





Hth,
--
Shitansh Vaghela
 

rakko said:
the only thing you need to do is make sure the mux switches when both clocks are low then you are gauranteed not to have any glitches.
Click to expand...

To check whether there will a glitch or not we will perform the clock gating timing check on the select line of mux.
 

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