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How can I convert Verilog code (gatelvel) to Schematic?

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ahmad_abdulghany

ahmad_abdulghany

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convert verilog to schematic

Hi,

I've a large Verilog code in the gate level (after synthesis) is it possible to convert it to a more readable format like block level that is read from any schematic viewer?

Thanks,
Ahmad
 

converting verilog to schematic capture

Hi, You can try debussy or verdi
 

schematic to verilog code

verilog -> logic synthesis -> verilog in (cadence tool )

or use debussy but not synthesis
 

Hi,

Can any one send me the software or tool name which will convert verilog code to RTL(schematic) view???

Please reply as early as possible.
Thanking you,
 

I think you can use the software Design Vision from Synopsys to convert verilog to schematic.. :)
 

If you want to implement your design in FPGA u can use Xilinx ISE. Load ur design and synthesise by doible clicking "Syntheise"...............After synthesising u can view the RTL schematic.....Press the "+" button of "Synthesise" ..........and press "RTL schematic".....U can refer to Xilinx Documentation

If u want to implement ur design as ASIC use Synopsys DC.............there is a shortcut to view the RTL schematic...........refer to manual
 

Mr.vivek
I have simulated in Xilinx ISE and synthesized it too. after that I got two schematics RTL and technology .... If I want to use the schematic for another circuit in mentor graphics which one to use????
awaiting your reply,


sincerely ,
M.S.Chandra Sekhar
 

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