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  1. #1
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    verilog $setup

    the program works fine in behaviorial mode but when i sythesize and try to simulate the the gates version i have a problem with my testbench code as it gives me the following error, and i dont get any output(everything is 0):

    "/CMC/kits/artisan_rcim/tsmc18.v", 23815: Timing violation in prog_counter_testbench.prog_counter_inst.\latch_co unter_reg[2]
    $setuphold<hold>( negedge G &&& (SandR == 1):702, negedge D:702, 1, 1 );

    ive tried to use initial clock /2 and increase the cycle time but it still gives me the same error, i really dont know what else try pls help.i wanted to totally eliminate the latch from my original program code but my supervisor says theres no problem with the program code but its the testbench that is faulty as im trying to read more than one register at the same time the clock iput changes, but idf that were so, then clock/2 should have skewed the clock time wrt to the rest of the circuit. im confused
    (the initial program is a programmable timer that functions in this mode as a countdown timer)
    //**********testbench******************************* ******
    module prog_counter_testbench ();
    reg reset, CE, write_CR, clk, load;
    reg [7:0] data_in;
    wire data_out;
    reg [7:0] data;
    parameter cycle = 40;
    initial
    begin
    clk = 0;
    forever #cycle clk = ~clk;
    end
    initial
    begin
    reset = 0;
    CE = 1;
    write_CR = 0;
    load = 0;
    data_in = 0;
    #cycle
    // setting for reset to 1
    reset = 1;
    repeat (2) #cycle;
    reset = 0;
    #cycle;
    // to set CE to low to enable chip
    CE = 0;
    #cycle;
    // load values into the counter
    data = 8'hfa;
    load_counter(data);
    // write_CR values into control register
    // to enable counter and to put counter in mode 0
    // which is a one shot mode
    data = 8'b00000100;
    write_CR_CR(data);
    #2000;
    $stop;
    end
    task write_CR_CR;
    input [7:0] data;
    begin
    write_CR = 1;
    data_in = data;
    repeat (2) #cycle;
    write_CR = 0;
    data_in = 0;
    #cycle;
    end
    endtask
    task load_counter;
    input [7:0] data;
    begin
    load = 1;
    data_in = data;
    repeat (2) #cycle;
    load = 0;
    data_in = 0;
    #cycle;
    end
    endtask

    prog_counter prog_counter_inst (reset, CE, write_CR,
    data_in, clk, load, data_out);

    initial
    begin
    $display ("Executing in Mode 0");
    $monitor ("clk %b reset %b CE %b load %b data_in %b write_CR %b data_out %b", clk, reset, CE, load, data_in, write_CR, data_out);
    end
    endmodule

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  2. #2
    Advanced Member level 3
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    verilog hold time

    new code for your design?



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