rickmhusa
Newbie level 3
dropout questione
Hi,
Frequently, we see papers state the drop-out voltage of a regulator is 200mV when Iout(max) = 100mA. If I understand it correctly, it means the Vds(sat) of the power MOS (let's assume a PMOS power MOS is used) is 200mV. Also |Vgs| - |Vth| = Vov of the power MOS is nearly equal to 200mV when Iout = 100mA. Am I correct? If so, when Iout = 0, the Vov of the power MOS will be very small. In fact, it may will be in a sub-threshold region, since the device size is large and Iout is small. If the power MOS is in the sub-threshold region, how will the regulator regulate the output as Iout = 0?
I am interested in the design of a low drop-out regulator, and I am just a beginner. Perhaps someone who is expert on this topic can help me out. Thanks alots.
Hi,
Frequently, we see papers state the drop-out voltage of a regulator is 200mV when Iout(max) = 100mA. If I understand it correctly, it means the Vds(sat) of the power MOS (let's assume a PMOS power MOS is used) is 200mV. Also |Vgs| - |Vth| = Vov of the power MOS is nearly equal to 200mV when Iout = 100mA. Am I correct? If so, when Iout = 0, the Vov of the power MOS will be very small. In fact, it may will be in a sub-threshold region, since the device size is large and Iout is small. If the power MOS is in the sub-threshold region, how will the regulator regulate the output as Iout = 0?
I am interested in the design of a low drop-out regulator, and I am just a beginner. Perhaps someone who is expert on this topic can help me out. Thanks alots.