I am working on a Sigma Delta ADC project, and need to decide the bit-width of the digital filter. My filter has 4 stages, the first is CIC and the bit width is 29 bits according to the OSR. My final filter output is only 24 bits. So this means the other 3 FIR filters need to reduce 5 bits in total. If my input is 4-bits signed and output is 24 bits signed, OSR=256, how to decide the bit reducation of each the 3 filters. What's the impact of the performance due to the bit-width reduce. Any comments?