vlsi_freak
Full Member level 2
Hi All,
Does verilog allows to use generate statements inside another generate statement.
I have a requirement as shon below,
generate if (A >1) // A is a top level generic
generate for (i=0; i<10; i=i+1)
begin : START
logic.....
end
endgenerate
endgenerate
The above gives errors while compiling. Any other option to use generate inside another generate.
regards,
freak
Does verilog allows to use generate statements inside another generate statement.
I have a requirement as shon below,
generate if (A >1) // A is a top level generic
generate for (i=0; i<10; i=i+1)
begin : START
logic.....
end
endgenerate
endgenerate
The above gives errors while compiling. Any other option to use generate inside another generate.
regards,
freak