Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Glitch with MUX output

Status
Not open for further replies.

yx.yang

Full Member level 4
Joined
May 29, 2008
Messages
236
Helped
49
Reputation
98
Reaction score
46
Trophy points
1,308
Location
ZhuHai, GuangDong, China
Activity points
2,661
mux glitch

I have a problem with MUX, can somebody kindly help me?
Let's take 2 to 1 MUX for example:
In RTL code, you may write:
wire a1, a2;
wire out;
wire sel;

assign out = (sel == 1'b0)? a1 : a2;

The question is:
If sel is constant 1'b0 and a1 is also stable. But a2 may change cycle
by cycle. For the real circuit(after place and route), when a2 changes, is there
any glitch on the MUX output pin "out"?

Note: You really don't know how the synthesis tool will implement this function and the delay for each path may different after place and route.


If there will exit glitch on "out", would you please give me a example; If there is no glitch on "out", would you please give a brief prove.

How about the same question for 4 to 1 / 8 to 1 (or N to 1) MUX?


Thanks.
 

mux 4-1 rtl

I think there should not be any glitch since a2 will be a non-controlling signal (given that select is a constant 1'b0) for a 2:1 MUX.

Also a better way to write the mux would just be "assign out = sel ? a2 : a1;". There is no need to make life more complex with more verbose code.

The question doesn't make sense for 4:1 or N:1 MUX since then you will have multiple select signals.
 

glitching mux

pgbackup said:
I think there should not be any glitch since a2 will be a non-controlling signal (given that select is a constant 1'b0) for a 2:1 MUX.

Also a better way to write the mux would just be "assign out = sel ? a2 : a1;". There is no need to make life more complex with more verbose code.

The question doesn't make sense for 4:1 or N:1 MUX since then you will have multiple select signals.

Hi, pgbackup: Thanks for your reply.

Let's take 4 : 1 MUX for example:
wire [1:0] sel;
wire a0, a1, a2, a3;
reg out;

always @(*)
case(sel)
2'h0: out = a0;
2'h1: out = a1;
2'h2: out = a2;
2'h3: out = a3;
endcase

The question is: if sel == 2'h0, and a0 is stable; while a1/a2/a3 may change cycle by cycle. When a1/a2/a3 changes, is there any glitch on the MUX out pin "out".

Thanks.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top