yx.yang
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mux glitch
I have a problem with MUX, can somebody kindly help me?
Let's take 2 to 1 MUX for example:
In RTL code, you may write:
wire a1, a2;
wire out;
wire sel;
assign out = (sel == 1'b0)? a1 : a2;
The question is:
If sel is constant 1'b0 and a1 is also stable. But a2 may change cycle
by cycle. For the real circuit(after place and route), when a2 changes, is there
any glitch on the MUX output pin "out"?
Note: You really don't know how the synthesis tool will implement this function and the delay for each path may different after place and route.
If there will exit glitch on "out", would you please give me a example; If there is no glitch on "out", would you please give a brief prove.
How about the same question for 4 to 1 / 8 to 1 (or N to 1) MUX?
Thanks.
I have a problem with MUX, can somebody kindly help me?
Let's take 2 to 1 MUX for example:
In RTL code, you may write:
wire a1, a2;
wire out;
wire sel;
assign out = (sel == 1'b0)? a1 : a2;
The question is:
If sel is constant 1'b0 and a1 is also stable. But a2 may change cycle
by cycle. For the real circuit(after place and route), when a2 changes, is there
any glitch on the MUX output pin "out"?
Note: You really don't know how the synthesis tool will implement this function and the delay for each path may different after place and route.
If there will exit glitch on "out", would you please give me a example; If there is no glitch on "out", would you please give a brief prove.
How about the same question for 4 to 1 / 8 to 1 (or N to 1) MUX?
Thanks.