Hi folks,
I have synthesized AES (Advanced Encryption Standard ) verilog core downloaded from www.opencores.org. It has a module called sbox.v which is instantiated more than once (actually 20 times) in the top level. To save area and gate count what i did was i synthesized the whole design by setting don't touch on the sbox.v design so that multiple instances are not created. I was able to successfully synthesize the design by creating 1 instance of sbox.v. The gate of the design was 3000. I was also able to perform post synthesis simulation with SDF back annotation without any problem.

Then i went to perform P&R using Synopsys Astro and did the P&R successfully.I generated the post layout SDF file and also generated the post layout verilog file.

Now the problem is that the post layout verilog file is flattened and the whole design hierarchy has been removed. This means all my efforts to save area have gone futile because the verilog netlist has 60,000 gates. All the 20 instances of sbox.v have been blown up and the gate count has jumped from 3000 to 20*3000 = 60,000. The SDF file that is created is also not compatible with post synthesis netlist because it corresponds to the flattened post layout netlist.

Is there any way i can maintain the hierarchy in the layout to save gate count?

Please let me know if it does not make sense to you.

Thanks a lot.

With Kind Regards