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  1. #1
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    multicycle sdf simulation

    I am getting this error in post synthesis verilog simulation of AES core. Design Compiler synthesized the design correctly without any errors with a period constraint of 5ns( 200 MHZ) .

    When i ran post synthesis verilog simulation, even with a period of 20ns (4 * 5 ns), i still get get the following error because of which the output is xxxxxxxxxxxxxxxxxxxxxxx.


    Error: tsmc18t.v(6551): $hold( posedge CK &&& (flag == 1):30 ns, negedge D:30 ns, 500 ps );
    # Time: 30 ns Iteration: 2 Instance: /test/u0/u0/r0/\out_reg[31]


    Note that when i increase the period to 30ns (i.e. by a factor of 6), the error goes away. But i am wondering why is there an increase in the frequency by a factor of 6. This makes me think that Design Compiler grossly underestimates the clk periode?

    Can some body help please so that i am able to run the post synthesis verilog simulation close to the frequency of 200 MHZ(i.e. 5ns) reported by Design Compiler.

    I also checked with PrimeTime and it also had no problem with period constraint of 5ns.




    Thanks a lot in advance

  2. #2
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    simulation post synthesis in verilog errors

    What is the timescale you are using in simulation environment. This may not be the problem, but just in case.



  3. #3
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    output_delay synthesis

    `timescale 1ns/10ps



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  4. #4
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    mytechface

    this is very strange, if the only problem is this hold time, i don't think increasing clock period will be of any help.

    are you simulating with SDF? if not, you should.


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  5. #5
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    verilog hierarchy timescale

    mytechface!

    You are awesome. You caught the problem at its root. I was not simulating the sdf thats why i was having such a problem. With sdf every thing is fine

    But still there is a SLIGHT gap between the frequency reported by PrimeTime and the frequency with which i am able to run post synthesis simulation.
    PrimeTime reports 8ns period to be OK without any violations while doing post synthesis simulation i have to increase the period to 14ns so that i dont get xxxxxxxxxxxx at the output. This means i can not run post synthesis simulation with the exact period reported by PrimeTime.

    Can you tell why this gap exists and does it make sense?



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  6. #6
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    design compile set_dont_use all

    how many clock domains do you have? if you have more than 1, it is possible signal crossing the clock domains are going X.

    another possible thing is, did you add any false path or multicycle path in your STA?


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  7. #7
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    iit018

    mytechface

    I did not add any false path or multicycle path. Its a design i downloaded from www.opencores.org. I dont have much clue about false paths and multicycle paths in the design. My guess is there are no multicycle paths since there are no multipliers or arithmetic blocks in the design. About false paths i am not sure.

    But i have only one clock domain.

    What do you suggest? Should i search for these? or there are other alternatives?



  8. #8
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    verilog post synthesis

    what is the timing on the interfaces... i.e. ports of your designs?

    can you check how the design was constrained on it's input ports. let's say you have a signal A going into your design. what is the delay of A relative to clock? what is it is STA and how is it driven in your sims. you might be driving it too early (HOLD) or too late (SETUP).


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  9. #9
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    driving signal in 2 clock domain verilog

    I am attaching constraint files for you to look at.

    The on chip and off chip delays are 2ns with respect to clock with a period of 8ns. You can see these in top_level.tcl

    I am not able to understand your question about simulation. I mean i don't know how to delay the input signal in simulation?



  10. #10
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    verilog synthesis problem

    can you check the testbench you are using to run the sims. the module that is "driving" the signals... those should have "correct" delay wrt the clocks else you are going to have some timing problems. if it is too little you will have hold problems, too much, setup problem.

    based on your description of the problem, the fact that you are able to "fix" it by increasing the clock period suggests that you have a SETUP issue. so i would suggest that you look for these incoming signals and check if they are being delayed too much. if they are, try changing it to 2 ns as you used in STA (sorry i can't open the rar in this machine as of now).

    by the way, is your netlist post-CTS (clock tree synthesis) or are you still using ideal clock?


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  11. #11
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    Re: post synthesis verilog simulation error

    I am pasting the constraint files. I am using the ideal clock with some skew as shown below.

    #################################################
    #File: top_level.tcl
    #

    set CLK_PORT [get_ports clk]

    set CLK_PERIOD 8.0

    set WC_SKEW 0.25

    set RST "rst"

    set DRV_CELL BUFX12
    # set DRV_CELL BUFX2 #for iit018.db

    set DRV_PIN "Y"

    set OUTPUT_LOAD [load_of typical/BUFX12/A]
    #set OUTPUT_LOAD [load_of iit018_stdcells/BUFX2/A] # for iit018.db

    set INPUT_DELAY 2

    set OUTPUT_DELAY 2

    set ALL_INS_EX_CLK [remove_from_collection [all_inputs] [get_ports clk]]

    reset_design


    create_clock -period $CLK_PERIOD -name my_clock $CLK_PORT

    set_dont_touch_network [get_clocks my_clock]

    set_clock_uncertainty $WC_SKEW [get_clocks my_clock]

    set_driving_cell -lib_cell $DRV_CELL -pin $DRV_PIN $ALL_INS_EX_CLK

    set_load $OUTPUT_LOAD [all_outputs]

    set_input_delay -max $INPUT_DELAY -clock my_clock $ALL_INS_EX_CLK

    set_output_delay -max $OUTPUT_DELAY -clock my_clock [all_outputs]

    set_wire_load_model -name tsmc18_wl10

    ################################################


    ###############################################
    #File:script.tcl
    #This file needs top_level.tcl for synthesis


    set LIB_BASE /opt/home/username/tsmc018/
    set STDCELL_LIBRARY slow

    set search_path {./ LIB_BASE}
    set link_library [list {*} [format "%s%s" [format "%s%s" $LIB_BASE $STDCELL_LIBRARY] {.db}]]
    set target_library [format "%s%s" [format "%s%s" $LIB_BASE $STDCELL_LIBRARY] {.db}]
    set synthetic_library = "dw_foundation.sldb"

    set DESIGNS_LIST {aes_sbox aes_rcon aes_key_expand_128 aes_cipher_top}

    foreach module $DESIGNS_LIST {
    read_verilog $module.v
    }

    current_design $module
    link
    check_design
    set_flatten true
    uniquify
    source -echo top_level.tcl

    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/EDFF*}]
    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/SDFF*}]
    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/SEDFF*}]
    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/SDFF*}]
    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/SDFF*}]
    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/SDFF*}]
    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/TLAT*}]
    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/RF*}]
    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/*XL}]
    set_dont_use [format "%s%s" $STDCELL_LIBRARY {/*X1}]



    #/* optimize the area */
    set_max_area 0.0


    set fix_hold_with_extra_margin {YES}
    set fix_hold_extra_margin 0.02
    set_fix_hold [list clk]


    compile -scan -incremental_mapping -map_effort high

    report_constraints -all_violators -verbose
    report_timing


    write -format verilog -hierarchy -output $module.v2
    write -format ddc -hierarchy -output $module.ddc
    write_sdc $module.sdc
    write_sdf $module.sdf

    redirect aes_syn.rpt {report_constraint -all_violators}
    redirect -append aes_syn.rpt {report_timing}



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  12. #12
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    post synthesis verilog simulation error

    ok, yeah you did have 2 ns on the input delay... so once your simulation testbench matches this (i.e. all inputs come out 2ns after clock edge) then your sims should match your STA freq closely.


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  13. #13
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    post synthesis verilog simulation error

    Let me try this.

    But first hats off to you mytechface.

    Lots of appreciation and kind regards.



  14. #14
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    post synthesis verilog simulation error

    It works !!



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