DEBUG THIS CODE...IF POSSIBLE

#if debug

kindly debug the following code if u can:
its about a counter which counts feed_in pulses for 1sec. the clock used as a reference is 50MHz.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY feedback IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
feed_in : IN std_logic;
feed_out : OUT std_logic_vector(7 DOWNTO 0)
);
END feedback;


ARCHITECTURE rtl OF feedback IS

-- Signals
SIGNAL tcount : std_logic_vector(7 DOWNTO 0);
SIGNAL pcount : std_logic_vector(7 DOWNTO 0);
SIGNAL feed_count : std_logic_vector(7 DOWNTO 0);
SIGNAL Count_out : std_logic_vector(7 DOWNTO 0);
SIGNAL Counter_out1 : std_logic_vector(25 DOWNTO 0);
SIGNAL Count_total : std_logic_vector(7 DOWNTO 0);

BEGIN


--Counter for 1sec time

Counter_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Counter_out1 <= (others=> '0');
elsIF clk'event AND clk = '1' THEN
IF Counter_out1 = "10111110101111000010000000" THEN --50M cycles/sec => 50MHz clock
Counter_out1 <= (others=> '0');
ELSE
Counter_out1 <= Counter_out1 + 1;
END IF;
END IF;
END PROCESS Counter_process;


--counter for number of pulses in 1sec

Counter_pulse : PROCESS (feed_in, reset)
BEGIN
IF reset = '1'THEN
pcount <= (others=> '0');
IF Counter_out1 = "10111110101111000010000000" THEN
Count_total <= pcount;
pcount <= (others=> '0');
ELSIF feed_in'event AND feed_in = '1' THEN
pcount <= pcount + 1;
END IF;
END IF;
END PROCESS Counter_pulse;

--incomplete task:scalling the output count with x6.to make: 40 to 240
Count_out <= Count_total;
--final output
feed_out <= Count_out(7 DOWNTO 0);

END rtl;

Click to expand...

debug code 26

koolslash said:

kindly debug the following code if u can:
its about a counter which counts feed_in pulses for 1sec. the clock used as a reference is 50MHz.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY feedback IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
feed_in : IN std_logic;
feed_out : OUT std_logic_vector(7 DOWNTO 0)
);
END feedback;


ARCHITECTURE rtl OF feedback IS

-- Signals
SIGNAL tcount : std_logic_vector(7 DOWNTO 0);
SIGNAL pcount : std_logic_vector(7 DOWNTO 0);
SIGNAL feed_count : std_logic_vector(7 DOWNTO 0);
SIGNAL Count_out : std_logic_vector(7 DOWNTO 0);
SIGNAL Counter_out1 : std_logic_vector(25 DOWNTO 0);
SIGNAL Count_total : std_logic_vector(7 DOWNTO 0);

BEGIN


--Counter for 1sec time

Counter_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Counter_out1 <= (others=> '0');
elsIF clk'event AND clk = '1' THEN
IF Counter_out1 = "10111110101111000010000000" THEN --50M cycles/sec => 50MHz clock
Counter_out1 <= (others=> '0');
ELSE
Counter_out1 <= Counter_out1 + 1;
END IF;
END IF;
END PROCESS Counter_process;


--counter for number of pulses in 1sec

Counter_pulse : PROCESS (feed_in, reset)
BEGIN
IF reset = '1'THEN
pcount <= (others=> '0');
IF Counter_out1 = "10111110101111000010000000" THEN
Count_total <= pcount;
pcount <= (others=> '0');
ELSIF feed_in'event AND feed_in = '1' THEN
pcount <= pcount + 1;
END IF;
END IF;
END PROCESS Counter_pulse;

--incomplete task:scalling the output count with x6.to make: 40 to 240
Count_out <= Count_total;
--final output
feed_out <= Count_out(7 DOWNTO 0);

END rtl;

Click to expand...

Click to expand...

Hi
Count_total will be 50M when counter_out1 is 10111110101111000010000000.
the same value is passed into feed_out.

Tell me one thing is it necessary to write this statement like this
feed_out <= Count_out(7 DOWNTO 0);

feed_out and count_out are having the same width.....then why to write in the above fashion.

Added after 1 minutes:

count_toatl will be 10000000 when counter_out1 will be 50M.else it again comes to 0

thanx. i appreciate for ur concern.
well the last few statements are to be edited. so i will definitely remove this.

But my main concern was that:
i want to count pulses received at feed_in in 1sec.
i wrote this code but it is not working.Need some one to debug it.

koolslash said:

thanx. i appreciate for ur concern.
well the last few statements are to be edited. so i will definitely remove this.

But my main concern was that:
i want to count pulses received at feed_in in 1sec.
i wrote this code but it is not working.Need some one to debug it.

Click to expand...

If you can post your sample trace/testbench code as well, maybe someone can point you what's wrong.

Ajeetha, CVC
www.cvcblr.com

i haven't written any test bench. i solve my problems with force command.

anyhow, if there is any other solution to solve the matter [count number of pulses in 1sec], then do tell me.

this code was only a try from me. may be i m thinking the problem in a wrong way.

LOOKING forward for you ppl's help.

FINALLY I FIGURED OUT THE PROBLEM AND SOLVED IT

hi
what is the meaning of following statement

Counter_out1 <= (others=> '0');

Click to expand...

thank you

Counter_out1 <= (others=> '0');

Click to expand...

means that:
make every bit to zero, of counter_out1.
its another form of counter_out1 => '00000000';
when u dont want to write this string of zero or u r not sure of typing exact number of zeros then the above qouted method is good to use.

i hope i answered ur question appropriately...

hi
thank you koolslash
yes every thing clear as crystal

hey cool.. wht exactly was the problem?

sir i have problem related with verilog HDL.whenever i simulate my program, it shows an error "Too many parameter assignments in instance ' ' of module ' '" .plesase solve the problem as soon as possible.

Counter_pulse : PROCESS (feed_in, reset)
BEGIN
IF reset = '1'THEN
pcount <= (others=> '0');
IF Counter_out1 = "10111110101111000010000000" THEN
Count_total <= pcount;
pcount <= (others=> '0');
ELSIF feed_in'event AND feed_in = '1' THEN
pcount <= pcount + 1;
END IF;
END IF;
END PROCESS Counter_pulse;

the problem is you need to add another Count_total <= pcount; to the else statement above

or you can't get a total if its elsed and not if's or its just 0

maybe you dont make proper endifs ??? directives most language's needs this
or there is no 'clean' process tree ....

Counter_pulse : PROCESS (feed_in, reset)
BEGIN
IF reset = '1'THEN
pcount <= (others=> '0');
END IF;
IF Counter_out1 = "10111110101111000010000000" THEN
pcount <= (others=> '0');
ELSIF feed_in'event AND feed_in = '1' THEN
pcount <= pcount + 1; Count_total <= pcount;
END IF;
END PROCESS Counter_pulse;

above all treat each major separate event especialy reset
as a function of its own
'has presedence' and dont mix the reset threads with the clocking counts events or you'll get BIG problems with heating and latency of count

plan your process tree on good old paper with a pen
code read's from top to bottom so make your functions read in this fashon
if you want mixed threads
as an analergie
remember hierachie of ritualistic events {built in to society as hard/routines} and your own function/s {own thought/soft routines {usualy variables based}


its always better to 'reset at the end' and correct the count if needed
it uses another few mpu cycles buts its worth it to mask the reset with a reset if recieved this helps to check for strange clock 'spurios' events
if you mix hard and soft routines you should use some sort of outcome masking like this
especialy when dealing with reset using a 'reset' flag is also a good idea as its more reusable and have a hard and soft routine set

BEGIN...

{
SET UP PINS AND VARS JUMP TO CLOCK

{{{
HARD...
triggers hard's and softs
}}}

{{{{
SOFT....
triggers hard if needed with respect to clock
}}}}

{{
BEGIN...
CLOCK
interrupt gen for hard 'DEAL WITH RESET AND OTHER PINS LIKS CS DATACLK ETC' ...never END... just dont add it
}}

}

END



Counter_pulse : PROCESS (feed_in, reset)
BEGIN
IF Counter_out1 = "10111110101111000010000000" THEN
pcount <= (others=> '0');
ELSIF feed_in'event AND feed_in = '1' THEN
pcount <= pcount + 1;
END IF;
IF reset = '1'THEN
pcount <= (others=> '0');
END IF;
Count_total <= pcount;
END PROCESS Counter_pulse;

above all things

if you write code that begins and ends a global routine
this is bad practice as you leave security holes
you begin the clocking event and never end just begin within the begining
so the code runs all the time
if you begin and end a whole rotuine set all the time an mpu has to 'fetch' instruction from other areas of the chip
watch for this one or youll get the the problem that you can't get good timing
a thing most people forget with small pic 12 etc that depend on a closed timings{clocking} loop... {never tied a BEGIN and dont add the end???}

Added after 54 minutes:

rishabh said:

sir i have problem related with verilog HDL.whenever i simulate my program, it shows an error "Too many parameter assignments in instance ' ' of module ' '" .plesase solve the problem as soon as possible.

Click to expand...

if you difine a module and load it at runtime
its given a parathetic status string

ie an allocation of variables
variables have peramiters as do difined flags etc

you simply difined something wrongly with a larger amount of variable than the director will allow

moduleparathetis (hard {1,2,3,4,5}soft{1,2,3,4,5,6})

callmoduleparatheticinstance(hard{1,2,3,4,5,6}soft{1,2,3,4,5,6})


eh euuuu you called too many hard rotuines or in this case hard and soft
i would blame your poor error message its not an easy one for sure to find
and would take just a simple parse to fix and give more granularity and :. clarity to the return message your given

you should complain that the assembler is stuip to the makers of the software
it like telling you the atom is wrong somewhere in your diamond and its a problem every compiler ive ever used has

what a pathetic error message...."Too many parameter assignments in instance ' ' of module ' '"

er you have here and its it here and here is what is wrong popup ... correct button to correct the statement systax with a choice not to and to edit etc...

a module is easy to scan on load so i beleve companies do this on public release assemblers to slow down 3rd party developers


nothing more....

maybe using

systax error
and syntax error is a good idea as a clear divide