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  1. #1
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    import system verilog

    Hi Guys,

    I need to import a VHDL package into a SystemVerilog Envirnment. Does Anybody know how this can be done?

    import package::*

    and

    `include "package.vhd"

    and

    instantiating the package as a unit in the sv file

    DO NOT WORK


    Thanks

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  2. #2
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    package in vhdl

    the guide should lead the solution!



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  3. #3
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    include vhdl package in system verilog

    Which guide????

    Thanks



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  4. #4
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    get system verilog constant in vhdl

    Depends on the tool you use. If you use Questa, yes, use:

    Code:
    vcom -mixedsvvh
    and then the data types, constants declared in VHDL are visible in SV. There are some restrictions as well, read the user guide.

    Other tools may not support this, a WA will be to rewrite them in SV (can potentially use a script).

    HTH
    Ajeetha, CVC
    www.cvcblr.com



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