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Vhdl integer error????????????

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non-standard ieee type integer

port(
x:in std_logic;
y:in integer range 0 to 32;
z:eek:ut integer range 0 to 32;
w: out std_logic);

For the simple above entiy I get the following error:

Line 17: ERROR, Non-Standard IEEE type "integer", used for port "y"
Line 17: ERROR, VITAL Top-Level port "y" has a "integer" type mark that does not denote a type/subtype declared in package std_logic_1164
Line 17: WARNING, Dimension/Range definition "(0 to 32)", for "y", does not comply to descending order convention

HOW CAN I SOLVE??
 

vhdl integer range

Using integer types for top level ports may be supported by your VHDL tool. In synthesizable designs, the mapping of integer to port bits is implementation dependant.

As a more simple reason, you possibly didn't import a numeric library.
 

vhdl integer

If I am correct,Integer declared in the port declaration part is not synthasizable.
You can declare as a std_logic_vector in the port and convert it.
 

vhdl integer declaration

Or perhaps try defining a type or subtype name in a package

package MyComponentPack is
subtype MyInt_t is natural range 0 to 32;
end package;

and use it wherever you need that kind of signal

use work.MyComponentPack.all;
...
port (
...
y : in MyInt_t;
...
 

vhdl descending order

Is it synthesizable??
 

integer types vhdl

I don't see that using a package with a type definition changes anything. Integer type in top level ports is supported by some synthesis tools, e.g. A.ltera Q.uartus, but apparently unsupported by some others. That's O.K., because the VHDL standard doesn't require it, as far as I understand.
 

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