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calibre lvs error "ne" CMOS 0.13um and boundary pr

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calibre lvs error

Hi
I have two problems:
-first I have an error on calibre lvs "ne" for "named error" I changed the "M1pn" to "M1pt (M1pintext)" and "label" but the netlist layout is always different to the netlist source,how can I resolve this problem?
-second, when I do a "gen from source" for two or four pixels(for example) and I connect them(vdd! gnd! psel rst), I do "connectivity--show incomplete nets" the picture shows me that I don't have connected nothing of them(I think that the problem is my boundary)?

Thanks
 

calibre cmos

could you be more specific and put as much info so that we can help you.e.g. lvs report, sreen capture of layout etc.

cheers
 

0.13um cmos

I found the solution, it was a problem on my pin (the use of M1pn instead of M1pt),I changed it with "q" for properties instead of update components and net

cheers
 

pr boundary in layout

i have a problem with calibre too. at LVS it says ports are missing and didnt identify any of ports. while in layout the ports are present. what this problem could be. its also saying that power and ground net are missing, while they are also there. can you help me at this

Added after 41 seconds:

and another question, can i perform XRC without doing LVS?
 

calibre lvs missing port error

M1pn instead of M1pt
 

calibre lvs layout ports missing in the source

In Calibre (depends how the deck is written though) ports are identified by Text label.
Usualy label must be on a pin layer. The port is created at the place of the label justificaztion. (that little tiny dot when you move the label)
 

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