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45 nm layout challenges - help me in the general issues

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shashikumar.22

shashikumar.22

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yield dfm

Hi
I am going to design layout of some 45 nm. Can anybody help me in the general issues related to it.

thanks!!!!
 

45nm

As per my knowledge, Going to down technologies following are the some of the issues we critically find out....

1. WPE
2. LOD
3. Density.
4. Lot of DFM and Yield related rules.
5. More conservative OPC rules.

These are upto 65nm. But coming to particularly 45nm, In some of the foundries I heard there are problems with Dummy poly usage and different types of spacings for different types of Power metals...etc... But I am not sure exactly what are the critical issues...!!!
 
45 nm layout challenges

add to that NBTIin PMOS, HCI (hot carrier injection) in NMOS effec,litho hot spots...routng has to be more litho friendlythan 90nm or previous..... in addition to PBTI... at 45 leakage is also more prevalent and path resistance (parasitics) is more critical due to scaling
 
Re: 45 nm layout challenges

:D thanks varma and Deepak. Can anybody please provide me the preventive measure for that NBTIin PMOS, HCI (hot carrier injection) in NMOS effec , i mean as far as layout is concern
 

Re: 45 nm layout challenges

deepak242003 said:
add to that NBTIin PMOS, HCI (hot carrier injection) in NMOS effec,litho hot spots...routng has to be more litho friendlythan 90nm or previous..... in addition to PBTI... at 45 leakage is also more prevalent and path resistance (parasitics) is more critical due to scaling
Click to expand...

Deepak can you give more info about these effects that you have mentioned. Becuase I don't aware of these perfectly....Also try and mention the prevention techniques also...!!!
 

Re: 45 nm layout challenges

here is some information for NBTI.
 

Re: 45 nm layout challenges

Negative bias temperature instability (NBTI) is a very real issue for UDSM CMOS devices because of its deleterious effect on threshold voltage and drive current. Interestingly, when constant voltage stress is periodically interrupted (AC stress), the degradation recovers, making standard DC stress testing too pessimistic an estimate of lifetime. Through better modeling of actual device behavior and better understanding of the NBTI threat with continued device scaling, engineers can minimize the impact of NBTI on future devices.
 

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