Creating VCD using the lsi_dumpports command questions

lsi_dumpports

Hello everyone,

I was trying to dump a VCD for a design using the lsi_dumpports command. I needed to dump out the ports in the design as well as enables for bidirectional ports. The enable signals would be nets in submodules of the design. How do I use lsi_dumpports to create a VCD including all these? The reason I am confused is that if only the module name can be given to lsi_dumpports, how can the enable nets be dumped out?

Also, is there any difference between the lsi_dumpports and the dumpvars command?

Appreciate any help
Regards,
Jean

Creating VCD

I do not know about the lsi_dumpports command/pli; so the following about the VCD dump tasks defined in the verilog specification may not be useful.

A typical approach is as follow:
1) Create a VCD file
$dumpfile(<fileName>"
2) Specify variables (signals, ports, registers, etc.) to record (dump)
$dumpvars(<level>, <list of variables/modules>);
<level> = 0 --> All modules
<level> = 1 --> Limit to the current level, in ohter words, only the variables within the module(s) specified, and so on
4) If desired, limit the size of the VCD file:
$dumplimit(<fileSize>)
3) If desired, Stop/Pause/Resume dumping via:
$dumpoff;
$dumpon;
4) If desired, flush buffers to VCD file, preferably just before the end of simulation
$dumpflush;

Hope this helps!