CTS and skew control - clock skew balancing

clock skew balancing

Hi guys,

while using SoC encounter, I didn't quite understand a couple of options
you can provide the CTS engine with:

- clkgroup (the sinks of all clock root pins listed in a ClkGroup statement
will meet the maximum skew value set in the clock tree specification file.
Clock grouping inserts delays to balance the clocks, and attemps to meet clock
skew for all clocks.)

- MaxSkew (specifies the maximum skew between sinks (clock pins) )

Now, I've a design with different clock domains, let's say 4. Therefore I will have
4 different section per clock and within each section I have a MaxSkew parameter.
My understanding is that MaxSkew represents the skew between the sinks WITHIN that clock domain.

Whereas, ClkGroup should balance the skew between the 4 different clock domains.
Now my question is: how can I control the skew between those 4 domains? I want to relax the skew constrains between the 4 clock domains because I can use a synchronizer to balance the skew rather than adding buffers and delays in the clock tree.

Do you have any clue? Did I get the two parameters correctly?

Moreover, within the same clock domain, will an increment of MaxSkew imply
a frequency drop? (I assume: there's more skew, my final working frequency should drop)
Are those two things correlated in general?

Thanks a lot in advance!

cts local skew

Guys,

am I completely out of scope or the question is too funny?
Please give me any sort of feedback!

Thanks

Hi Ludan,
Please the CTS part in the SOC user guide.
Please find a sample clock spec there.
Clock grouping itself will help you balance skew across the different clock domains.
Placing the synchronizer, I hope u can do it in the rtl coding itself.

As you know, ideal skew is zero.
non zero skew is not like decrease in freq,
it might solve few violations, or might end up creating few violations.
violations in the sense setup and hold.

Please correct me if I am wrong.

Thanks,
Sowmya