omara007
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Hi Folks
It's been almost 2 hours now, since I started my synthesis process !! .. I feel like there is a problem !! .. I was expecting a run time around 20 to 30 mins max. It's just synthesis !! .. not the complete Bit Generation process !!!
I have a doubt regarding one thing .. in my design, I'm having one (VHDL) module that contains one big combinational process (i.e. not clocked process). I am expecting some of the code in this process to be interpreted as LATCHes .. could this result in a problem with the FPGA synthesis ? .. in fact, if you look at the circuit that should be generated from this process, you will find it input/output registered by the outside blocks it's connected to. For that, I didn't make it a clocked process, as I'm in need for every wasted clock cycle.
Please help regard.
It's been almost 2 hours now, since I started my synthesis process !! .. I feel like there is a problem !! .. I was expecting a run time around 20 to 30 mins max. It's just synthesis !! .. not the complete Bit Generation process !!!
I have a doubt regarding one thing .. in my design, I'm having one (VHDL) module that contains one big combinational process (i.e. not clocked process). I am expecting some of the code in this process to be interpreted as LATCHes .. could this result in a problem with the FPGA synthesis ? .. in fact, if you look at the circuit that should be generated from this process, you will find it input/output registered by the outside blocks it's connected to. For that, I didn't make it a clocked process, as I'm in need for every wasted clock cycle.
Please help regard.
