spectre_man
Newbie level 2
trace impedance
Hello,
I have a multilayer board (12 layers, might have to increase...read on) with multiple isolated grounds (returns).
It is an FPGA design, and all of the signals with critical impedance specs are FPGA-ground referenced digital I/O signals.
In my layer stackup, there are six pwr/gnd plane layers, but only one of these is FPGA-GND. It is a true plane layer (takes up entire board area).
The impedance calculations I'm getting from board vendors seem to be measuring the thickness of the dielectric between a signal on layer N and the NEAREST plane layer(s), not to the FPGA-GND layer to which the signal is referenced, even if that nearest plane layer(s) is (are) totally isolated from the signals in question. Does that make any sense?
If not, how should this be done? I imagined (perhaps incorrectly) that the trace WIDTH would be varied on each layer so that the impedance calculation (using the width on that layer, and the separation distance from the FPGA-GND layer) would come out to the spec (in this case 50 Ohm). If this is the case, that should be fairly simple. Is the impedance calc changed at all by the fact that there may be isolated metal plane layers between the critical trace and its reference plane? I can't find any trace impedance model that shows this, but in the real world on a multilayer board it seems crazy to require that the gnd plane (reference) always be adjacent to a routing layer containing signals referenced to that ground--every other layer would have to be a ground layer.
thanks,
Jude
Hello,
I have a multilayer board (12 layers, might have to increase...read on) with multiple isolated grounds (returns).
It is an FPGA design, and all of the signals with critical impedance specs are FPGA-ground referenced digital I/O signals.
In my layer stackup, there are six pwr/gnd plane layers, but only one of these is FPGA-GND. It is a true plane layer (takes up entire board area).
The impedance calculations I'm getting from board vendors seem to be measuring the thickness of the dielectric between a signal on layer N and the NEAREST plane layer(s), not to the FPGA-GND layer to which the signal is referenced, even if that nearest plane layer(s) is (are) totally isolated from the signals in question. Does that make any sense?
If not, how should this be done? I imagined (perhaps incorrectly) that the trace WIDTH would be varied on each layer so that the impedance calculation (using the width on that layer, and the separation distance from the FPGA-GND layer) would come out to the spec (in this case 50 Ohm). If this is the case, that should be fairly simple. Is the impedance calc changed at all by the fact that there may be isolated metal plane layers between the critical trace and its reference plane? I can't find any trace impedance model that shows this, but in the real world on a multilayer board it seems crazy to require that the gnd plane (reference) always be adjacent to a routing layer containing signals referenced to that ground--every other layer would have to be a ground layer.
thanks,
Jude