help, basic vhdl state machine with nexus 2

vhdl state machine

Hi
I have written the VHDL code below. The intended use is to have an state machine.
that starts from 0. When I use the switch and a operator it should store the switch
value and operator and go to state 1. Then if I press equal it should store a new
switch value and depending on which operator I have used calculate result etc.
But when I run it on my nexus 2 board it doest work as intended.
Please help me with suggested corrections in the code below.

process(state,operand,equal,switch,clk)
variable tal1, tal2: std_logic_vector(7 downto 0 );
variable result: std_logic_vector(15 downto 0 );
variable temp_operand: std_logic_vector(2 downto 0 );

begin

if rising_edge(clk) then

case state is

when s0 => if operand/="000" then
temp_operand:=operand;
dispx(7 downto 0 )<= switch(7 downto 0 );
dispx(15 downto 8 )<="11101110";
tal1:=switch(7 downto 0 );
state<=s1;

else
dispx(7 downto 0 )<= switch(7 downto 0 );
dispx(15 downto 8 )<="11101110";
end if;

when s1=> if equal='1' then
tal2:=switch(7 downto 0 );

case temp_operand is

when "100" => result:=("00000000"&tal1)+tal2;
dispx<=result;
state<=s2;

when "010" => result:=("00000000"&tal1)-tal2;
dispx<=result;
state<=s2;

when others => result:=tal1*tal2;
dispx<=result;
state<=s2;
end case;

else
dispx(7 downto 0 )<= switch(7 downto 0 );
dispx(15 downto 8 )<="11101110";
end if;


when s2 => if switch/=tal2 then
state<=s0;
else
state<=s2;
dispx<= result;
end if;

when others => state<=s0;
end case;
end if;
end process;

nexus 2 fpga

HI,

For any and all digital design at first glance it doesnt work than you have to check for power, if board gets properly power up and is power properly distributed among all comaponant ?

If this is ok then check for clk and reset. if your design gets clk and reset properly?

check it by assigning clk and reset to led or gpio (in case of gpio check with CRO or make led mechenism or any thing else whatever you feel better).

if this also is coming properly then there is problem in your design code.

to check where is problem in state machine .....
First thing you have to take care about full and parallel case state ment. is there d full case? and is there defaul case? these are necessary to prevent from latch and undesired state.

still problem is there then you have to simulate and debug that way. take care about simulation and synthesis misbihavior

Hth,
--
Shitansh Vaghela

nexus s2 codes

Thanks for replying
I have power and so on since my code is running but not properly. I believe it is
within the state description the problem is. I do not use any resent, since my code
should take care of “unwanted” states and “push” it to the state s0 as a starting
state. But I can’t "see" where the problem lies within the code I have written.

That’s why I asked for specific comments regarding my code.

HI,

unfortunately i have no experience with VHDL thats why i have given you direction. if it is in verilog then perheps i can help you.

If by convertor you can send me code in Verilog then i will see it. rightnow quite busy else i already have did it.

Added after 6 minutes:

Another suggetion ,

Try to make your FSM with two blocks one for sequential and another for combinational and also meke seperate block for output logik this way you can debug it more.

HTH
--
Shitansh Vaghela

Check out this one!

The code still dont work when I transfer its bitfile to the Nexus 2 board. The switch is connected to the buttons B18,D18 and E18 enabling to choose +, - or * as operand. The equal should be the button H13 on the board. The display shows the values from the switches G18 to R17, correctly. But after I press say "+" and thereafter gives the second number and press button for "equal" it dosent work. It dosent show the value. Cant "see" whats wrong with the code?
Any further suggestions?

Can I get the complete vhdl code?

The problem could be ...
You are using the push buttons B18, D18 and E18 without debouncing.
Checkout this ...
https://www.fpga4fun.com/Debouncer2.html

Hope this helps!