EdgeS
Newbie level 3
pulse generator verilog problem
Hi all,
I am a newbie in FPGA and Verilog. I am currently programming 2 pulse generators running at the same time using an external clock. I'm using Cyclone 2 on a DE2 board. I tried to write the codes from scratch and the simulation turn out exactly like what I wanted it to be. But the problem comes when I download the codes into the chip, I do not get any output. I'm using a 10Mhz clock.
My codes as below:
Need help from anyone to see where did I go wrong. I used to believe that once I have a simulation, the output should be the same. I was so wrong. As I'm still new, I may not have provided the correct/sufficient info. If you need any info please do tell.
Thanks a lot in advance. Any help at all is greatly appreciated.
p.s. As its still in draft, some input/output may not be in use yet.
Hi all,
I am a newbie in FPGA and Verilog. I am currently programming 2 pulse generators running at the same time using an external clock. I'm using Cyclone 2 on a DE2 board. I tried to write the codes from scratch and the simulation turn out exactly like what I wanted it to be. But the problem comes when I download the codes into the chip, I do not get any output. I'm using a 10Mhz clock.
My codes as below:
Code:
module pulgen2 (
reset_clk,
out_clk,
out_clk2,
count_ena,
count_clk
);
//-----Input Ports-----
input reset_clk;
input count_ena;
input count_clk;
//-----Output Ports-----
output out_clk;
output out_clk2;
//-Input Ports Data Type-
wire reset_clk;
wire count_ena;
wire count_clk;
//-Output Ports Data Type-
wire out_clk;
wire out_clk2;
//---Internal Registers---
reg [13:0] count;
reg reset_cnt;
reg temp_out1;
reg temp_out2;
//-Assign output to internal register-
assign out_clk = temp_out1;
assign out_clk2 = temp_out2;
//------Counter------
always @ (posedge count_clk)
if (reset_clk)
begin
count <= 0;
end
else if (count >= 10000-1)
begin
count <= 0;
end
else
begin : COUNT
while (count_clk)
begin
count <= count + 1;
disable COUNT;
end
end
//-Start and Stop Pulses-
always @ (posedge count_clk)
if (reset_clk)
begin
temp_out1 <= 0;
temp_out2 <= 0;
end
else if (count_clk)
begin
case (count)
8'h00000000 : temp_out1 <= ~temp_out1;
8'h00000002 : temp_out1 <= ~temp_out1;
8'h0000000F : temp_out2 <= ~temp_out2;
8'h00000015 : temp_out2 <= ~temp_out2;
endcase
end
endmodule
Need help from anyone to see where did I go wrong. I used to believe that once I have a simulation, the output should be the same. I was so wrong. As I'm still new, I may not have provided the correct/sufficient info. If you need any info please do tell.
Thanks a lot in advance. Any help at all is greatly appreciated.
p.s. As its still in draft, some input/output may not be in use yet.