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Pulse Generator Problem - I do not get any output

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EdgeS

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pulse generator verilog problem

Hi all,

I am a newbie in FPGA and Verilog. I am currently programming 2 pulse generators running at the same time using an external clock. I'm using Cyclone 2 on a DE2 board. I tried to write the codes from scratch and the simulation turn out exactly like what I wanted it to be. But the problem comes when I download the codes into the chip, I do not get any output. I'm using a 10Mhz clock.

My codes as below:

Code: 
module pulgen2 (
reset_clk,
out_clk,
out_clk2,
count_ena,
count_clk
);

//-----Input Ports-----
input reset_clk;
input count_ena;
input count_clk;

//-----Output Ports-----
output out_clk;
output out_clk2;

//-Input Ports Data Type-
wire reset_clk;
wire count_ena;
wire count_clk;

//-Output Ports Data Type-
wire out_clk;
wire out_clk2;

//---Internal Registers---
reg [13:0] count;
reg reset_cnt;
reg temp_out1;
reg temp_out2;

//-Assign output to internal register-
assign out_clk = temp_out1;
assign out_clk2 = temp_out2;



//------Counter------
always @ (posedge count_clk)
if (reset_clk)
  begin
	count <= 0;
  end 

else if (count >= 10000-1)
begin
count <= 0;
end

else
  begin : COUNT
	while (count_clk)
	begin
	count <= count + 1;
	disable COUNT;
    end
  end



//-Start and Stop Pulses-
always @ (posedge count_clk)
  if (reset_clk)
	begin
	temp_out1 <= 0;
	temp_out2 <= 0;
	end
  
else if (count_clk)
  begin
	case (count)
	  8'h00000000 : temp_out1 <= ~temp_out1;
	  8'h00000002 : temp_out1 <= ~temp_out1;
	  8'h0000000F : temp_out2 <= ~temp_out2;
	  8'h00000015 : temp_out2 <= ~temp_out2;
	endcase
  end
  
endmodule

Need help from anyone to see where did I go wrong. I used to believe that once I have a simulation, the output should be the same. I was so wrong. As I'm still new, I may not have provided the correct/sufficient info. If you need any info please do tell.

Thanks a lot in advance. Any help at all is greatly appreciated.

p.s. As its still in draft, some input/output may not be in use yet.
 

Pulse Generator Problem

Anyone can please verify if the code is correct? Now I'm confused whether my hardware is giving the problem or my codes itself.

Thanks a lot in advance.
 

Re: Pulse Generator Problem

Here is the corrected code....
Code: 
module pulgen2 (
                reset_clk,
                out_clk,
                out_clk2,
                count_ena,
                count_clk
                );
   
   //-----Input Ports-----
   input reset_clk;
   input count_ena;
   input count_clk;
   
   //-----Output Ports-----
   output out_clk;
   output out_clk2;
   
   //-Output Ports Data Type-
   reg   out_clk;
   reg   out_clk2;
   
   //---Internal Registers---
   reg [13:0] count;
   
   //------Counter------
   always @ (posedge count_clk)
     if (reset_clk) 
          count <= 0;
     else if (count >= 10000-1)
       count <= 0;
     else if (count_ena)
       count <= count + 1;

   //-Start and Stop Pulses-
   always @ (posedge count_clk)
     if (reset_clk) begin
        out_clk <= 0;
        out_clk2 <= 0;
     end else  begin
        case (count)
          13'h0000 : out_clk  <= ~out_clk;
          13'h0002 : out_clk  <= ~out_clk;
          13'h000F : out_clk2 <= ~out_clk2;
          13'h0015 : out_clk2 <= ~out_clk2;
        endcase
     end
endmodule
 

Pulse Generator Problem

Thanks a lot for the codes. I'd like to understand a few things. I need to tap the signal from the output but I can't do that with output as register isn't it? Don't I have to assign it as a wire instead?
 

Re: Pulse Generator Problem

In verilog it's not required!
 

    E

    EdgeS

    Points: 2
    Helpful Answer Positive Rating
Pulse Generator Problem

Its been a long weekend. Thanks for the advice. I'll try it out... Thanks again.
 

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