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Looking for Junior ASIC/VLSI Engineer

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felicia

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junior engineer + vlsi

Hi All,

We are looking for Junior ASIC/VLSI Engineer.
It is a permanent opportunity for a R&D center of a US company in Singapore.

Responsibilities:
• Design and verification of blocks

Requirements:
• BSEE + 1 year experience
• Proven experience with VLSI environment (Linux , simulators)
• Knowledge in verilog design and basic block flow
• Knowledge in C and basic test bench
• Experience with debug , RTL changes
• Familiarity with Synopsys tools - advantage
• Exceptional drive and motivational skills

If you are interested, please send your resume to felicia@uniconnect.com.sg

Thank you.
:D
 

junior vlsi engineer

hi,
i have master degree in microelectronics engineering and have 2 years experiencs in R&D based ic design center, also have experience on fabrication process, therefor find myself suiteable for backend design and DFT.
i have also seen your post regarding job for backend IC designer. while only thing contrary to your requirement is that i have experience on Mentor Graphics, not on cadence. So please respond with your feed back.
another thing im HIGHLY interested in these jobs
 

asic vlsi job singapore

Hi Felicia,
If the opening exists now,i would be interested.I feel i have already mailed my resume to you.Please let me know the updates.

Thanks
Nruthya
 

vlsi 2 yr exp 2009

Hi,
is this position still open
 

resumes for 1year experience in vlsi

Hi,

I would like to know if the opening is still there...
 

vlsi resume mentor

Hi,

Right now we are looking for backend engineers and verification engineers with at least 4-5 years of relevant experience & having experience in large SoC.
 

vlsi verification engineer in singapore

Hi, i have already send my CV to you, should i send it again if any new position is announced? or the one i already sent is enough and considered for any suitable position. thanx
 

asic junior engineer

Hello,

I am Computer Engineer (since 2006), graduated in Brazil and I have a master degree in Digital Telecommunications Systems from Telecom ParisTech (2008). I still worked with CADENCE and Synopsys tools to digital prototyping. I wok with microelectronics projects since 2004.

Best Regards,
Patricia Lira
 

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