Modelsim systemc port/signal names not found for submodules

systemc port

I have a model of a design I'm working on in SystemC. I'm trying to use Modelsim to debug it.

It currently consists of two submodules, each instantiated in the top level module. All of these are in their respective header files.

The top level module is then instantiated in a test.cpp file.


After compiling, linking, and starting vsim, the signals in the test.cpp file appear correctly. However, any of the signals/ports of my top level entity and the submodules are called "signal_1", or "port_1", etc.

I have SC_MODULE_EXPORT(toplevel), and tried with SC_MODULE_EXPORT(child1) (and for child2), but none of this helped.

Anyone have any suggestions?

I attached a screenshot illustrating what I'm referring to, which also has the console output from vsim.

Thanks,
baver

sc_module_export

do you have declare the port in the .c file?

modelsim view submodule signal

I've used sc_in/sc_out - is there another way they need to be declared?

(As a side note, compiling it against libsystemc works fine, so things seem connected properly)

modelsim signals not appearing in submodules

Hi baver,
In ModelSim, the compile, linking are not sufficient to say that the code is "compile-error free". Once the VSIM is loaded without error then only we can say it compiled properly. One suggession is `include the work library in your top level CPP file plus include all your design file names in the top level CPP file.

-Paul

Re: Modelsim systemc port/signal names not found for submodu

Try: vsim -novopt to start with. If it works, you may instead use:


–voptargs=+acc

and get better performance

HTH
Ajeetha, CVC
www.cvcblr.com