Verilog code for a register file and also a test bench error

Urgent Question

Hello there!

I am trying to write a verilog code for a register file and also a test bench but I
run the simulation it gives me error in test bench:
Lv RA,RB,RW,WriteEnable and BusW cannot be anet.

could any one help me?

this is the code

module reg_file(clk, rst, RA, RB, RW, WriteEnable, BusW, BusA, BusB);
input clk, rst;
input[4:0] RA, RB, RW;
input WriteEnable;
input[31:0] BusW;
output[31:0] BusA, BusB;
wire [31:0]x,Z;

//decoder to get i/p to the register
assign
Z[0] = (~RW[4]&~RW[3]&~RW[2]&~RW[1]&~RW[0]),
Z[1] = (~RW[4]&~RW[3]&~RW[2]&~RW[1]&RW[0]),
Z[2] = (~RW[4]&~RW[3]&~RW[2]&RW[1]&~RW[0]),
Z[3] = (~RW[4]&~RW[3]&~RW[2]&RW[1]&RW[0]),
Z[4] = (~RW[4]&~RW[3]&RW[2]&~RW[1]&~RW[0]),
Z[5] = (~RW[4]&~RW[3]&RW[2]&~RW[1]&RW[0]),
Z[6] = (~RW[4]&~RW[3]&RW[2]&RW[1]&~RW[0]),
Z[7] = (~RW[4]&~RW[3]&RW[2]&RW[1]&RW[0]),
Z[8] = (~RW[4]&RW[3]&~RW[2]&~RW[1]&~RW[0]),
Z[9] = (~RW[4]&RW[3]&~RW[2]&~RW[1]&RW[0]),
Z[10] = (~RW[4]&RW[3]&~RW[2]&RW[1]&~RW[0]),
Z[11] = (~RW[4]&RW[3]&~RW[2]&RW[1]&RW[0]),
Z[12] = (~RW[4]&RW[3]&RW[2]&~RW[1]&~RW[0]),
Z[13] = (~RW[4]&RW[3]&RW[2]&~RW[1]&RW[0]),
Z[14] = (~RW[4]&RW[3]&RW[2]&RW[1]&~RW[0]),
Z[15] = (~RW[4]&RW[3]&RW[2]&RW[1]&RW[0]),
Z[16] = (RW[4]&~RW[3]&~RW[2]&~RW[1]&~RW[0]),
Z[17] = (RW[4]&~RW[3]&~RW[2]&~RW[1]&RW[0]),
Z[18] = (RW[4]&~RW[3]&~RW[2]&RW[1]&~RW[0]),
Z[19] = (RW[4]&~RW[3]&~RW[2]&RW[1]&RW[0]),
Z[20] = (RW[4]&~RW[3]&RW[2]&~RW[1]&~RW[0]),
Z[21] = (RW[4]&~RW[3]&RW[2]&~RW[1]&RW[0]),
Z[22] = (RW[4]&~RW[3]&RW[2]&RW[1]&~RW[0]),
Z[23] = (RW[4]&~RW[3]&RW[2]&RW[1]&RW[0]),
Z[24] = (RW[4]&RW[3]&~RW[2]&~RW[1]&~RW[0]),
Z[25] = (RW[4]&RW[3]&~RW[2]&~RW[1]&RW[0]),
Z[26] = (RW[4]&RW[3]&~RW[2]&RW[1]&~RW[0]),
Z[27] = (RW[4]&RW[3]&~RW[2]&RW[1]&RW[0]),
Z[28] = (RW[4]&RW[3]&RW[2]&~RW[1]&~RW[0]),
Z[29] = (RW[4]&RW[3]&RW[2]&~RW[1]&RW[0]),
Z[30] = (RW[4]&RW[3]&RW[2]&RW[1]&~RW[0]),
Z[31] = (RW[4]&RW[3]&RW[2]&RW[1]&RW[0]);

assign x= WriteEnable & Z ;

always @(posedge clk)
begin
if (rst)
y = 0;
else if (x)
y = BusW;
end
mux MUX1 (y,BusA,RA);
mux MUX2 (y,BusB,RB);

endmodule

/*Register
module beh_register (clk,rst,y,x,BusW);
input clk,rst;
input [31:0]x,BusW;
output [31:0]y;
reg [31:0]y;
always @(posedge clk)
begin
if (rst)
y = 0;
else if (x)
y = BusW;
end
endmodule*/

// mux
module mux(inp,Out,select);
input [31:0]inp;
input [4:0] select;
output Out;
reg Out;
always @ (inp or select)
case (select)
5'b00000: Out = inp[0];
5'b00001: Out = inp[1];
5'b00010: Out = inp[2];
5'b00011: Out = inp[3];
5'b00100: Out = inp[4];
5'b00101: Out = inp[5];
5'b00110: Out = inp[6];
5'b00111: Out = inp[7];
5'b01000: Out = inp[8];
5'b01001: Out = inp[9];
5'b01010: Out = inp[10];
5'b01011: Out = inp[11];
5'b01100: Out = inp[12];
5'b01101: Out = inp[13];
5'b01110: Out = inp[14];
5'b01111: Out = inp[15];
5'b10000: Out = inp[16];
5'b10001: Out = inp[17];
5'b10010: Out = inp[18];
5'b10011: Out = inp[19];
5'b10100: Out = inp[20];
5'b10101: Out = inp[21];
5'b10110: Out = inp[22];
5'b10111: Out = inp[23];
5'b11000: Out = inp[24];
5'b11001: Out = inp[25];
5'b11010: Out = inp[26];
5'b11011: Out = inp[27];
5'b11100: Out = inp[28];
5'b11101: Out = inp[29];
5'b11110: Out = inp[30];
5'b11111: Out = inp[31];
endcase
endmodule

module reg_testbench;

reg [31:0] BusA,BusB;
wire clk, rst;
wire[4:0] RA, RB, RW;
wire WriteEnable;
wire[31:0] BusW;

reg_file stmcrct(clk, rst, RA, RB, RW, WriteEnable, BusW, BusA, BusB);
initial
begin

BusW=32'b00000000000000000000111111111111 ;
WriteEnable=1'b1;
RW=5'b00000;
#10
BusW=32'b00011000000111000000111111111111 ;
WriteEnable=1'b1;
RW=5'b00001;
#10
WriteEnable=1'b0;
RA=5'b00000;
RB=5'b00001;
end
initial
$monitor ("BusW=%b\nBusA=%b\nBusB=%b\n",BusW,BusA,BusB);
endmodule

Urgent Question

In your testbench, when you have port mapped the design, u have declared :

reg [31:0] BusA,BusB;
wire clk, rst;
wire[4:0] RA, RB, RW;
wire WriteEnable;
wire[31:0] BusW;

Change it to :

wire [31:0] BusA,BusB;
reg clk, rst;
reg[4:0] RA, RB, RW;
reg WriteEnable;
reg[31:0] BusW;