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design compiler + contraints + 2 clocks

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research235

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Dear all

I am working on making a .sdc file from synthesis. in my design theare are 2 clocks.

now my question is how to define the relation between the clocks in .sdc file for the following condition

-- Block A gets input at rising edge of CLK 1
-- Block B gets as the input frm Block A o/p on falling edge of CLK 2

So is there a way to define the relation between the rising edge of CLK1 and Falling edge of CLK 2 as this imp for block B to get valid input from Block A.

Thank you in advance

Sing
 

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