How to deal with the layout of a circuit with large current?

Hi, the currents of my circuit are large, from 10mA to 60mA. Could someone give me some suggestion about what I should note when I do the layout design. Thanks!

Can you elaborate what circuit is it ? Most of the time
it depends on your devices .. for example LDO can drive even more current than this like upto 500 mA or so .. in that case you use large devices .. uses parallel path for the currents .. use thicker metals .. which fits
your electromigration bill ..

HTH
Raduga

Calculate the metal width required. Then try to see what are the metal levels you are supposed to use. This depends on the process chosen, area constraints. Depending on the above factors stack the metals.

Regards,
Sandeep

Re: How to deal with the layout of a circuit with large curr

Thanks to all of you! But what does parallel path mean? Does that mean I should use two metal levels to connect the devices instead of one metal level?

each metal layer has a current density capacity (current per one micron width) mentioned in one of the documents of the process. The thicker metals (thickness is not the same as width) on the top can carry more current for the same width. Use multiple (parallel) metal layers to add the capacity. But be sure to use a lot of vias at both ends , even they have current densities.

Re: How to deal with the layout of a circuit with large curr

hi

high current circuit , that mean more heat will be generated. don't place the circuit that sensitive to heat near to high current circuit like bandgap.

Re: How to deal with the layout of a circuit with large curr

lily1981216 said:

Thanks to all of you! But what does parallel path mean? Does that mean I should use two metal levels to connect the devices instead of one metal level?

Click to expand...

As said the use of metal level depends entirely on the floorplan and area constraints.
If say the plan is to use only M1 and M2 for signal routing, and M3 and M4 for power routing.
Then you need to check how to achieve all of these in the area specified. If not we need to either increase the block area or get more number of metals to achieve the current carrying density.

Regards,
Sandeep

Re: How to deal with the layout of a circuit with large curr

for large current circuits the metal layer width should be wide, as wide as it wont suffer from electromigration.

electromigration has to be kept in mind while doing layout of high current circuits.

For a large current circuit you need to take care of IR drop and Electromigration. First of all you have to use large width of metal lines so that the current capability is there and other thing is the total resistance of the current path (eg. large lengths should be avoided) should be in limits so that the IR drop is minimal.

check wiht part if drawing more current and calculate teh width accordingly...... if the current is too large use two or more metal one below other connected wiht vias.... to handle large current in less space..

Re: How to deal with the layout of a circuit with large curr

Please make sure the metals are wide enough not only to satisfy the EM checks but also the IR drop on the routing. if there is space constraint you can route it on more than one metals but make sure you put enough vias b/w diff metals.

Re: How to deal with the layout of a circuit with large curr

jt_rf said:

Please make sure the metals are wide enough not only to satisfy the EM checks but also the IR drop on the routing. if there is space constraint you can route it on more than one metals but make sure you put enough vias b/w diff metals.

Click to expand...

In most analog circuits, IR drops will a much bigger concern than EM or current density rules. In many cases, you will have to use A LOT of metal to minimize IR drops!

Re: How to deal with the layout of a circuit with large curr

In addition to earlier useful suggestions:

Try to achieve/guarantee a uniform current density in the metal - by making metal wider in areas with higher current and narrower in areas with lower current (metal tapering - like top metal fingers in power devices).

It's rare when a metal shape carrying a high current is a straight line - very often it is a curved path, connecting a circuit/device with another part of the circuit or with a metal wirebond/bump/leadframe. In this case, try to avoid making sharp bends (smooth them out, make them having larger radius of curvature).

Ultimately - the rules of thumb are useful, but may not provide a 100% guarantee that there are no problems. Use software tools to simulate current flow and voltage drop on the metal lines - and use this software to get an insight into physics of current flow in your structures (many effects may not be obvious until you simulate them and visualize the results) and to optimize the layouts.

See picture below illustrating a high current density (current crowding) in structures with sharp metal bends. Current crowding may lead not only to electromigration or IR voltage drop problems, but also to a localized current heating and associated thermo-mechanical reliability problems (cracking etc.).

Re: How to deal with the layout of a circuit with large curr

but , I have a problem , for the MOS technology, there is a large area for the Power MOSfets, and the metals are not only one layer(at least 2 layers), how should we arrange the metal? (for the current ?)

Re: How to deal with the layout of a circuit with large curr

chudong said:

but , I have a problem , for the MOS technology, there is a large area for the Power MOSfets, and the metals are not only one layer(at least 2 layers), how should we arrange the metal? (for the current ?)

Click to expand...

There was a discussion on metal layouts for power devices:



The top metal layers may have trapezoidal / triangular shape for reduced resistance (and/or to achieve constant current density), or other shapes - depending on the package and wirebonding constraints.

I attach a pictures of typical top metal layout in power MOSFET devices.

Max

Hi,
See the DRM for the current carring capability and decide the width of the desired design. parallel path means stacking of metals to adup the current .
but always make it to have better connection.

Re: How to deal with the layout of a circuit with large curr

It depends upon what components r u using? Give seperate ground path to components like LCD,ADC,DAC. (i.e avoid looping of gnd paths).

Just to add,

Current division/current divider rule is the root concept.