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Interleaved boost PFC

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eem2am

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interleaved pfc

Mains connected Switch mode power supplies often have a boost PFC stage at the front end.

Sometimes an interleaved boost PFC stage is used. Do you know why the interleaved boost is used?

Is it just because it allows increased power and lowers input ripple current?….or are there other reasons for interleaving?
 

interleaved boost pfc

Is it just because it allows increased power and lowers input ripple current?….
Aren't these properties reason enough?
 

interleaved boost

other advantages would be the reduced output current ripple (so bulk capacitor size can also be reduced).
the magnetics are also "distributed" so it's easy to manage the temperatures..
it increases the efficiency not only in full load, but also in light load (to do this, it's need to disable the other rail(s) during partial load.)
interleaving requires smaller EMI filters.
(the reduce input ripple current also minized or elimated the use of differential mode EMI filter.)
 

capacitor ripple current in an interleaved pfc

other advantages would be the reduced output current ripple (so bulk capacitor size can also be reduced)
Cause the idealized PFC output current is a full wave rectified mains frequency sine (plus some switching frequency ripple), the capacitor dimensioning is mainly governed by the acceptable 100/120 ripple amount. Additional bypass capacitors for switching frequency ripple may be smaller, of course.

In high power applications, an interphase transformer with suitable designed leakage inductance is often used instead of two individual inductors for two-phase boost converters. It allows a reduction of overall magnetics size.
 

pfc ripple current

the disadvantage now will be on the controller side..
it's more complicated than the single rail PFC..
but there's already controller ICs available in the market for this kind of topology,
like for TI, they have ucc28070 and ucc28060..


Cause the idealized PFC output current is a full wave rectified mains frequency sine (plus some switching frequency ripple),...
i thought, ideal PFC output current should be a DC current ? :?:
(i'm also aware that it's impossible (pure DC output) to meet w/ the existing topologies)
 

interleave pfc

thought, ideal PFC output current should be a DC current ?
No it can't be. But my previous statement also wasn't fully correct.

Consider an ideal PFC and an undistorted mains (sinusoidal) grid voltage. To achieve PF=1, the input current must have sine waveform and no phase shift. The momentary value of input power is
Code:
Pin = Vpeak*Ipeak*sin²(ωt) = 0.5*Vpeak*Ipeak*(1+cos(2ωt))
It has a double mains frequency ripple, but as a clean sine, not a full-wave rectified waveform. Asuming an almost constant DC bus voltage, Iout has the same waveform as the input power. The calculation uses a black-box PFC function and doesn't depend on it's topology.

As another comment, an ideal three phase PFC has a constant momentary input power and no 2nd mains harmonics ripple in output current. The bus capacitors have to be dimensioned for switch frequency ripple and dynamic load variations only.
 

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