Hold fix issue - hold violation problem

Hold fix issue

Hi All,

i am having issue in doing hold fix.
the path is input to register path.
hold violation is -0.640ns.
and hold margin is 0.410ns.

can anyone guide me how to fix this?

Thanks in advance.

Re: Hold fix issue

try to increase the delay in the data path by buffer or delay cell insertion.
also u can try to downsize the cells in the data path.

Hold fix issue

check your input delay constraint in sdc,maybe it's un-resonable.

Re: Hold fix issue

Thanks xinsu & praneshcn,

I checked the data_path and there is only one buf in the data_path.

i will reconfirm the sdc input delay constraint.

Regards.

Re: Hold fix issue

hi,

my 2 cents,

* Is there any specific reason to have such a huge hold margin of around 400ps?
if you reduce this then your problem would be simpler to solve or less buffers.
* Do you checked whether clock tree information is there for the input port or modelled, usually the capturing register will have the clock tree values but the port would not have so.
* Check your capture register clock tree , how big it is , is it reasonable number or huge .
* Either you can add data delay, in the data path, as you say that there is hardly one cell , then adding a delay should not be an issue , or you need to reduce the register clock tree, this would have impact in other places and this be touched or done at the lost resort when your hands are totally tied.
* Check your input delay numbers (as mentioned) whether it is reasonable.

https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/solvesetupholdviolation.html

myprayers,
https://www.vlsichipdesign.com
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Re: Hold fix issue

you can also try to insert some buffer!