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DFT question concerning ATPG

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Vincent Girard

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scan atpg dft

Hi guys,

I have some questions concerning ATPG process with TetramaX,
As you know during ATPG process the tool try to generate patterns using all
available scan cells in the design, but let's focus on what is happening during capture :

If the data that should be captured by a scan flop comes from an other scan flop,
which is working with another scan clock with potential skew between the two scan flops
then this data is considered as X by the tool preventing any timing issue that would make the pattern
fail during simulation.

Is that correct ? Then if so, how is the combo logic that need to be observed thru this scan flop tested.

thanks
 

In my opinion, durning the APR process, the tool will not only automaticly optimaze the Q to D path but also optimize the Q to SI path, so the skew will not affect the scan path after timing optimization.
 

Actually this depends on the clock tree, if the second scan clock edge comes after the first flop capture there will be no issue if a capture is done. But the ATPG tool doesn't have this information, for basic scan ATPG tool everything is supposed to toggle with a zero delay.

What do u mean by optimization ? Does that mean that scan insertion tool can manage this kind of issue?

Maybe someone who has already faced this issue with Tetramax could answer.

thanks ,
 

You are talking about shift or capture?

Vincent Girard said:
Hi guys,

I have some questions concerning ATPG process with TetramaX,
As you know during ATPG process the tool try to generate patterns using all
available scan cells in the design, but let's focus on what is happening during capture :

If the data that should be captured by a scan flop comes from an other scan flop,
which is working with another scan clock with potential skew between the two scan flops
then this data is considered as X by the tool preventing any timing issue that would make the pattern
fail during simulation.

Is that correct ? Then if so, how is the combo logic that need to be observed thru this scan flop tested.

thanks
Click to expand...
 

Hi my friend,

I'm talking about capture. No matter what happens during shift.

The question is how combinational logic is tested when it depends on a flop that can capture data,
and propagates to an observation point which is another scan flop ?


friendly,
 

And these two FFs are in different functional clock domain?

Vincent Girard said:
Hi my friend,

I'm talking about capture. No matter what happens during shift.

The question is how combinational logic is tested when it depends on a flop that can capture data,
and propagates to an observation point which is another scan flop ?


friendly,
Click to expand...
 

Hi wizard,

Yep ! That's it!

The flops are in two different clocks domains ( The path that is captured crosses two clocks domains )


Thx for reply.
 

In most cases, cross domain logic are little. So the coverage loss is little.

Are you sure X will be captured? I don't think so. I think until you tell the tool that's false path or mutli-cycle path it will not think it's X. The tool can make a mistake because there is no timing info but there may be some options you can tune. I'm not sure of this. Please have a try.


Vincent Girard said:
Hi wizard,

Yep ! That's it!

The flops are in two different clocks domains ( The path that is captured crosses two clocks domains )


Thx for reply.
Click to expand...
 

Is it stuck-at testing or at-speed testing you are talking about? If stuck-at, though the FF belong to two different clock domains functionally, during scan they will receive the same test clock (same clock used for both shift and capture) Paths between these two clock domains are not treated as false (X) by the tool and a capture pulse will be applied in both domains simultaneously enabling detection of stuck-at faults across the 2 domains. You need make sure that the testclock is balanced across these 2 domains by STA. Since the testclock for stuck-at is normally of slow frequency, clock balancing typically should not be a big challenge.

-Divya
 

And during transition test, the tool still will not treat it as X if the two clocks are applied sequentially.
If the two clocks are applied simultaneously then these paths will be treated as X spurces.

Clocks will be applied sequentially when the pattern targets these type of faults.
Clocks might be pulsed simultaneously if disturbed clock grouping is allowed.


-Ankit.
 

Hi,

+

The question is specific to the at-speed testing for sure.

Simple answer is
1. If you can balance the clock skews, u can test the combo logic between the clock domains. (pulsing all the clocks during capture)
2. If not (why!!), u can not do nothing. Just get the top up coverage after pulsing the individual clocks during capture. In this case u cannot test the combo logic between the clock domains. That is why total at-speed coverage lesser than that of stuck-at.

-Sunil B
 
Last edited:

You cannot put these 2 flops in the same scan chain.
 

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