ramsvlsi
Newbie level 4
site:www.edaboard.com clock recovery pll
hi,
in my design received data in any of these formats nrz-l,m,s or Bi_phase l,m,s.
receiver knows which format it receiving. input frequency range 20KHz to 30Mhz
but receiver dont know which frequency it receiving from different transmitters, how can we extract clock from this.
generally by using combinational logic we extract basic clock from the NRZ data, and then we applied to PLL for phase correction. iam using virtex-5 PLL IP Core. it asking for input frequency.
but here input frequency is unknown (any of 20Khz to 30Mhz) . give me idea how to implement the CDR.
thaku
hi,
in my design received data in any of these formats nrz-l,m,s or Bi_phase l,m,s.
receiver knows which format it receiving. input frequency range 20KHz to 30Mhz
but receiver dont know which frequency it receiving from different transmitters, how can we extract clock from this.
generally by using combinational logic we extract basic clock from the NRZ data, and then we applied to PLL for phase correction. iam using virtex-5 PLL IP Core. it asking for input frequency.
but here input frequency is unknown (any of 20Khz to 30Mhz) . give me idea how to implement the CDR.
thaku