[SOLVED] errors while running Tmax during DRC

drc rules tetramax

Hi everyone,
I am getting some errors while running Tmax during DRC:
How to overcome these errors..


DRC> set drc /home/student1/sk4xilinx/proj4/proj4stil.spf
run drc
------------------------------------------------------------------------------
Begin scan design rules checking...
------------------------------------------------------------------------------
Begin reading test protocol file /home/student1/sk4xilinx/proj4/proj4stil.spf...
Error: Line 10 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "a" is not a netlist pin). (V5-1)
Error: Line 11 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "b" is not a netlist pin). (V5-2)
Error: Line 12 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "c" is not a netlist pin). (V5-3)
Error: Line 13 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "clk" is not a netlist pin). (V5-4)
Error: Line 14 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "d" is not a netlist pin). (V5-5)
Error: Line 15 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "e" is not a netlist pin). (V5-6)
Error: Line 16 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "f" is not a netlist pin). (V5-7)
Error: Line 17 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "sen" is not a netlist pin). (V5-8)
Error: Line 18 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "fout" is not a netlist pin). (V5-9)
Error: Line 19 (/home/student1/sk4xilinx/proj4/proj4stil.spf), unresolved reference (Signal "test_si" is not a netlist pin -- Too many errors; parsing terminated). (V5-10)
End parsing STIL file /home/student1/sk4xilinx/proj4/proj4stil.spf with 10 errors.
Error: Design rules checking failed: cannot exit DRC command mode. (M100)

Re: TetraMax Help...

First of all, maybe you can check if the design (Verilog gate-level netlist, .v) is consistent with the SPF(proj4stil.spf) used.

TetraMax Help...

I also am getting the same errors. The name of the .stil file and that of the netlist is same. And all the signals, a,b ,c clk etc are indeed pins in the netlist and are also there in the .stil file. What else do I need to check in the .stil file? I am a novice.
Please reply.