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  1. #1
    Newbie level 3
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    Nanosim Help!

    I am using nanosim for postlayout simulation. The vector file is generated from the vcd file produced during postlayout netlist simulation.

    However, when i used this vector file together with my HspiceD netlist, the output waveform from nanosim is just the waveform output stored in the vector file.

    Any idea how I can view the real output waveform based on the input test vectors in the vector file?

    Many thanks

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  2. #2
    Full Member level 2
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    Nanosim Help!

    you can use the same testbench which used for post layout netlist simualtion for nanosim rather than the VCD file. I guess input test vectors are not driving it.
    BTW is it DFT simulation?



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  3. #3
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    Re: Nanosim Help!

    How do I use the testbench directly? I have yet to explore that option.

    It is jus the simulation that I used to verify the timing and functionality of my chip.



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  4. #4
    Full Member level 2
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    Nanosim Help!

    you can run the verilog testbench and the design in the .sch (spice) by running nanosim with vcs.

    Added after 4 minutes:

    look at this post https://www.edaboard.com/viewtopic.p...628&highlight=



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