Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to readback from FPGA

Status
Not open for further replies.
amitjagtap

amitjagtap

Full Member level 5
Joined
Jan 10, 2007
Messages
304
Helped
42
Reputation
84
Reaction score
36
Trophy points
1,308
Activity points
3,273
readback fpga

hi all
i need to know the procedure for reading back conguration file of FPGA...
anyone knows how to do this....
Thanking you....
 

readback fpga bitstream

Hi amit,
It might not be easy to read the configuration file from FPGA. However it is somewhat possible to read the configuration file which is stored in configuration PROM. (from which FPGA copies to configuation file).

See what is the interface between these two (FPGA & configuration PROM). See if any ISP tool supports reading from PROM.


Regards,
RAM
 

xilinx read back

Hi
Can you please tell us what you are trying to do?
Read the configuration file for what?
thanks
 

impact readback

Chipscope can read back the configurations
 

fpga xilinx readback

Xilinx's Impact software allows reading back some FPGA bitstreams, but it also allows disabling read back to protect the bitstream.
 

readback to ram

It is a bit hard as it is not allowed on most FPGAs I use but what do you need it for. I have to also take it that you are trying to copy some proprietary IP
 

xilinx impact reading bitstream

I don't understabd some of the contributions. If we're talking of FPGA with RAM based configuration and external configuration memory, the configuration can be read out from the memory in most cases and always captured at the configuration interface. Configuration readout from the FPGA isn't provided with most FPGA (except e.g. Xilinx Virtex devices) to simplify the hardware rather than for security reasons.

Some FPGA families, e.g. some &#65ltera Stratix and Xilinx Virtex have a bitstream encryption option, in this case the configuration bitstream is worthless without knowing the key stored inside the FPGA.
 

xilinx impact readback

FvM said:
I don't understabd some of the contributions. If we're talking of FPGA with RAM based configuration and external configuration memory, the configuration can be read out from the memory in most cases and always captured at the configuration interface. Configuration readout from the FPGA isn't provided with most FPGA (except e.g. Xilinx Virtex devices) to simplify the hardware rather than for security reasons.

Some FPGA families, e.g. some Altera Stratix and Xilinx Virtex have a bitstream encryption option, in this case the configuration bitstream is worthless without knowing the key stored inside the FPGA.
Click to expand...

One thing deserves to be mentioned here, is that not the same device that runs the unencrypted bitstream can run the encrypted one. The option must be provided by the very chip you are using. I faced this situation with Lattice semiconductors ECP2M-50.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top