Please help me with ATPG using the encounter test

tsv-016

Hi guys,
Please help me. When I using Encounter Test to do ATPG, lots of
warning came out, and they are all the same with the attached partial
log file but different register names, as the result the fault coverage of the
generated test pattern is only about 6%, could anybody please help me
solving this problem or tell me what is wrong. Thanks very much!

PS. The scan chain seems was correctly connected, because the reported
register numbers in the scan chain are the same with what I want.



############# Part of the Log file

Clock input pin u_zip_reg.IO.dff_primitive.master.PO2DCLK on memory
element block u_zip_reg.IO.dff_primitive.master.PO2DCLK is OFF (at logic
zero) when in the Test Inhibit state.

Clock input pin u_zip_reg.IO.dff_primitive.slave.PO2DCLK on memory
element block u_zip_reg.IO.dff_primitive.slave.PO2DCLK is OFF (at logic
zero) when in the Test Inhibit state.

############# my pin assignment file

assign pin=RESN_pad test_function= +TI; # global reset pad
assign pin=TMOD_pad test_function= 1TI; # test mode
assign pin=XTAL_pad test_function= -ES; # test clock && sys clock
assign pin=SCAN_ENABLE_pad test_function= +SE; # scan enable
assign pin=SCAN_IN_pad test_function= SI; # scan input
assign pin=SCAN_OUT_pad test_function= SO; # scan output

############# part of the netlist

SDFFSQx u_zip_reg( .SN(resn_in), .CK(sysCLK_scan), .D(n_4306),
.SI(n_7828), .SE(SCAN_sen), .Q(n_2708) );

BUF4 u0( .A(RESN_pad), .Y(resn_in) );
CLKBUF4 u1( .A(XTAL_pad), .Y(sys_clk) );
AND2X4 u2( .B(TMOD_pad), .A(XTAL_pad), .Y(test_clock) );
MUX2X u3( .SO(TMOD_pad), .B(test_clock), .A(sys_clk), .Y(sysCLK_scan) );
AND2X4 u4( .B(SCAN_ENABLE_pad), .A(TMOD_pad), .Y(SCAN_sen) );

fault coverage encounter test

can you provide the warning/Info with number like INFO TV00 ..

encounter atpg

santhosh007 said:

can you provide the warning/Info with number like INFO TV00 ..

Click to expand...

OK, thanks for your attention, I hope you can help me, the Log says :
WARNING (TSV-016): CLOCK input pin ... ... , (as I attached above)


I also has some other warning which I think may be ignored like
WARNING (TSV-193): In the Test Constraint state, three state net ADC_VBG_pad is sourced by block u_ADC_VBG_pad and u_ADC_VBG_pad which may simultaneously drive opposite values resulting in 3-state contention.

look at my comments below.

kenanou said:

santhosh007 said:

can you provide the warning/Info with number like INFO TV00 ..

Click to expand...

OK, thanks for your attention, I hope you can help me, the Log says :
WARNING (TSV-016): CLOCK input pin ... ... , (as I attached above)

This is becuase some latches are not transparent due to the inability to control the enable of latch. This can be wavied off if it is not fixeable. euqilvalent D6 in Fastscan(incase if you familiar)

I also has some other warning which I think may be ignored like
WARNING (TSV-193): In the Test Constraint state, three state net ADC_VBG_pad is sourced by block u_ADC_VBG_pad and u_ADC_VBG_pad which may simultaneously drive opposite values resulting in 3-state contention

this needs to fixed otherwise coverage drops. bus contention on the tristate busses thats why the tool not able to generate the patterns. thats the reason you seeing lower coverage

Click to expand...

santhosh007 said:

look at my comments below.

kenanou said:

santhosh007 said:

can you provide the warning/Info with number like INFO TV00 ..

Click to expand...

OK, thanks for your attention, I hope you can help me, the Log says :
WARNING (TSV-016): CLOCK input pin ... ... , (as I attached above)

This is becuase some latches are not transparent due to the inability to control the enable of latch. This can be wavied off if it is not fixeable. euqilvalent D6 in Fastscan(incase if you familiar)

I also has some other warning which I think may be ignored like
WARNING (TSV-193): In the Test Constraint state, three state net ADC_VBG_pad is sourced by block u_ADC_VBG_pad and u_ADC_VBG_pad which may simultaneously drive opposite values resulting in 3-state contention

this needs to fixed otherwise coverage drops. bus contention on the tristate busses thats why the tool not able to generate the patterns. thats the reason you seeing lower coverage

Click to expand...

Click to expand...

Thanks for your help , the fault coverage has arrived 88%, although not high enough yet , but the most serious problem has been solved, thanks again

For TSV-016, most likely, SN/RN is tied during test.

kenanou said:

santhosh007 said:

look at my comments below.

kenanou said:

santhosh007 said:

can you provide the warning/Info with number like INFO TV00 ..

Click to expand...

OK, thanks for your attention, I hope you can help me, the Log says :
WARNING (TSV-016): CLOCK input pin ... ... , (as I attached above)

This is becuase some latches are not transparent due to the inability to control the enable of latch. This can be wavied off if it is not fixeable. euqilvalent D6 in Fastscan(incase if you familiar)

I also has some other warning which I think may be ignored like
WARNING (TSV-193): In the Test Constraint state, three state net ADC_VBG_pad is sourced by block u_ADC_VBG_pad and u_ADC_VBG_pad which may simultaneously drive opposite values resulting in 3-state contention

this needs to fixed otherwise coverage drops. bus contention on the tristate busses thats why the tool not able to generate the patterns. thats the reason you seeing lower coverage

Click to expand...

Click to expand...

Thanks for your help , the fault coverage has arrived 88%, although not high enough yet , but the most serious problem has been solved, thanks again

Click to expand...