Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Using bit streams with Cyclone III

Status
Not open for further replies.
P

pdohm

Newbie level 1
Joined
Feb 18, 2009
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,290
Hello all,

I am having trouble trying to think of an effective way to take an incoming bit stream at some data rate, and store those values into memory to thus do operations on them. My first idea is to make an inital array of the size of data I want, say 32 bits, and then read at the input each time period, and store the value into the first spot of the array, the second period in the 2nd spot of the array and so on. Is there a more effective way to do this? I have programed FPGA's before, but nothing using incoming bit streams like this before. Would like to do this in VHDL also.

Thank you for the help.

Peter
 

Generally it's easy and can be coded straightforward in VHDL. However, there are some conditions not mentioned in your post, that should be known before starting a design:
- data rate
- what's the clock source for bit stream sampling?
- intended type of memory (e. g. internal RAM) and size
 

FvM is very right. i have designed some thing like this before.

i have one comment on your design. the way you are trying to store 32 bits in an array of 32 will need a 1-to-32 mux. which i think will be not a good design.

instead if you make a sift register of 32 and store in MSB and shift in each cycle. after 32 cycles you can read the data in parallel.

hopefully this will be helpful.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top