# how do i add a noise source in a circuit

1. ## noise source

helo ... i am working on a project which is the design of a lock in amplifier (phase sensitive detection system) .... my major aim of da project is to extract and amplify very weak signals buried in high levels of noise

my problem is .... how do i add a noise source in a circuit ... and how do i add the signal to the noise source ?

i will really appreciate the the help... thanks :)

•

2. ## noise source

you could use sinewaves with random frequency and phase or you could generate a noise file in matlab and use the vpwlf source in your schematics or write a verilog-a block that generates the noise.

•

3. ## Re: noise source

i am not familiar with matlab and as such i dont have much idea of how to create a noise file there .... not much sure about verilog either .... is there any electrical component which mighte solve the case ? or any other alternatives ? thanks

•

4. ## Re: noise source

This should work for spectre. Create a "functional" cellview called vnoise and copy and paste the following code. Create a new symbol and include it in your schematic.

`include "disciplines.vams"

module vnoise(out);
output out; electrical out;
parameter real period=1.0e-9;
parameter real vn=1.0;

integer x;

analog begin
@(timer(0.0,period))
x=\$random*vn;

V(out)<+transition(x,0.0,period);
end
endmodule

5. ## noise source

Sorry, I made a little mistake, this is a better code:

`include "disciplines.vams"

module vnoise(out);
output out; electrical out;

parameter real period=1.0e-9;
parameter real vn=1.0;

real x;

analog begin
@(timer(0.0,period))
x=\$random*vn/2147483647.0;

V(out)<+transition(x,0.0,period);
end
endmodule

you can also use

module vnoise(out);
output out; electrical out;

parameter real period=1.0e-9; //[1ns]
parameter integer seed=123;
parameter real mean=0.0;
parameter real std=1e-3; //[1mV]

real x;
integer y;

analog begin
@(initial_step)
y=seed;

@(timer(0.0,period))
x=\$rdist_normal(y,mean,std);

V(out)<+transition(x,0.0,period);
end
endmodule

--[[ ]]--