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  1. #1
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    pre layout simulation

    How is pre layout simulation and post layout simulations different?

    Also how are they different from functional verification?

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  2. #2
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    pre-layout simulation

    Pre-layout simulation is the one you use to check if your gate-level netlist (right after Synthesis) is functionally correct.but the post layout simulation "no longer in use" was to check that the gate-level netlist is still functionally equivalent the pre-layout one because you have added the clock tree, buffers,scan chains etc..

    In today's physical design flow, designers use functional verification as a way to check that the circuit function is right after synthesis.it uses mathematical formulations rather that dynamic simulation.it is much faster and more mature now.
    they also use the STA "statical timing analysis" to compensate the fact that functional verification can't check timing of the circuit....



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  3. #3
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    layout simulation

    Quote Originally Posted by mahmoudgazzar
    Pre-layout simulation is the one you use to check if your gate-level netlist (right after Synthesis) is functionally correct.but the post layout simulation "no longer in use" was to check that the gate-level netlist is still functionally equivalent the pre-layout one because you have added the clock tree, buffers,scan chains etc..

    In today's physical design flow, designers use functional verification as a way to check that the circuit function is right after synthesis.it uses mathematical formulations rather that dynamic simulation.it is much faster and more mature now.
    they also use the STA "statical timing analysis" to compensate the fact that functional verification can't check timing of the circuit....
    Actually even today several high end chips do significant post-layout simulation as the STA and formal equiv checking miss issues in areas of:

    1. Asynchronous boundaries
    2. Multiple clock domains

    etc. We infact have a half-a-day workshop focusing exclusively on this topic and has been attended in the past by folks from TI etc.

    Regards
    Ajeetha, CVC
    Next SV course starting in Feb 09 end. See:
    http://sv-verif.blogspot.com for details



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