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Possible to implement Dual port RAN with Single port RAM?

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what is port ran

The Dual port RAM is configured as Port A write, Port B read.. I assume it is working in such a way that read and write occur simultaneously, while read before write when two addresses equal.

Is it possible to emulate such behavior with Single port RAM? Duplicating RAM size is permitted (though it's larger than Dual Port)..
 

single port sram read write throughput

If its ok to use two SRAM's, U can implement with two single port SRAM's.
 

Re: Possible to implement Dual port RAN with Single port RAM

powerstar007 said:
If its ok to use two SRAM's, U can implement with two single port SRAM's.
Click to expand...

how to do that? can it be really done in a fashion that it's pin and timing compatible with dual-port RAM?

If the target RAM address size is small (say, N), I can write & read from alternative SRAM (A or B), at the same time use N registers to indicate which SRAM is to read which is to write..
 

u r approach is the one which is similar to my implementation...only thing which u need to take care is read and write at the same time with address locations and read and write with same address has to be bypassed.
 

Re: Possible to implement Dual port RAN with Single port RAM

powerstar007 said:
u r approach is the one which is similar to my implementation...only thing which u need to take care is read and write at the same time with address locations and read and write with same address has to be bypassed.
Click to expand...

is that the standard approach to achieve throughput of Dual Port RAM with single port RAMs? I am new to this and always open to new approaches to do things..

on the other hand, is it practical if the depth is 200k addresses? another piece is 4k addresses.. let's say using 4096 registers to differentiate which RAM address to write and which to read, will it become a laughing stock?
 

This is my idea ... i hope this is going to work!
No Need to have 2 - single port srams
Just use a single port sram with 2X clk speed.
2X clk is mapped to phase A and Phase B of the clk.
Always use phase A as write and Phase B as read



-
 

Re: Possible to implement Dual port RAN with Single port RAM

pra said:
This is my idea ... i hope this is going to work!
No Need to have 2 - single port srams
Just use a single port sram with 2X clk speed.
2X clk is mapped to phase A and Phase B of the clk.
Always use phase A as write and Phase B as read



-
Click to expand...

thank you.. in fact i have a clock of nearly 5X DPRAM access speed and the RAM speed can reach more than 5X.. so this idea in theory works but i need to inquire whether it fits into the project.. :D
 

In my design I used this logic and its working fine now.

But u need to check all the corner case scenarios too....

for example--- what is the read delay of SRAM n does it as has any limitations of wr/rd/wr of same address in consecutive clk cycles!
 

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