Reg excempting timing arc check

Hi,
I am having data flowing from a flop running at a higher frequency to a flop running at lower frequency. Its not a MCP. Let us say the time periods are Tx and Ty ( Tx < Ty)

I have an enable signal to allow the data transfer between theese flops. Say for every 'n' clocks once the data flow is stopped for a duration one clock cycle in order to avoid losing of launching data, as launching clock frequency is slightly higher than the capturing one. Which means PT need not to check the timing on that one perticular clock peroid for every 'n' clocks. Per say, the two (launch and capture) clock edges are 0.02 ns apart when the data transfer enable is deasserted. During the other cycles (when the datra transfer is asserted) the clock edges are seperated by morethan 0.02 say 1ns, 1.4 ns, 2ns, etc.

I want the timing check( setup) to happen on the edges seperated by 1ns. But not on the edges seperated by 0.02ns, as this is not a valid scenerio since there is no data transfer at that point. In other words I want the timing check to happen only when there is asserted enable.

Right now PT is looking for the least seperated edges i.e 0.02 and checking the timing on 0.02ns seperated edges and its failing, how can I excempt this check, so that the timing check happens on the correct edges (which are 1ns apart). Would like to remind you that this is not a multi cycle path.


Rgds.

Hi Polu,

I understood ur question like this, say CLK1 is higher frequency than the CLK2.

CLK1 is triggering the lauching flop, and CLK2 is triggering the capture flop. By default if u dont tell any relation for the two clocks in PT, It will calculate the LCM of two clocks, i.e, it will check for the most restictive edges.

say in this case 0.02 ns, but u want skip that timing check, check for the next edge, i.e. 1ns.

u can model this one as mcp constarint.

Thanks,
Chaitanya.

Hi chaitubek,
Thanks for your reply. But the clocks are not having any MCP relation...say clk1 is period is 1.4ns and clk2 period is 1.5ns.

Common multiples between these particular clocks comes out to be 0.1ns, 0.2ns, 0.3ns ...etc. Here LCM is 0.1ns....I want the check to be skipped for 0.1ns arc but the check should be on for the rest of the arcs 0.2ns, 0.3ns ..etc.

Notice that there is no genuine MCP value that can be given between these two clocks. If at all I give some big number (MCP ) timing arcs 0.2ns, 0.3ns etc won't be checked. I want those checks to happen as the data transmission between these clocks happens on every edge except on the edges that differed by 0.1ns (which is LCM).

Rgds,
Kiran Polu

Hi Polu,

As you told, the most restrictive edge between two clocks is 0.1 later 0.2 and 0.3

You want to skip 0.1 ns, remaining checkes u need to be done. If we r using mcp, it will chekc for more time.( not 0.2 and 0.3).

Here in this case, if we check for 0.2 ns, no need to check for 0.3ns and later.

This u can model as a set_max_delay constarint like following

set_max_delay 0.2 -from clk1 -to clk2

Hope this one solves the problem.

Thanks,
Chaitanya.

Since the clocks are asynchronous, you need to synchronize the signal to the receiving clock. You can use a two stage synchronizer clocked by the receiving clock. Since the launch clock is faster you would need to be sure not to send data every cycle or data will be lost. You do not need to check timing between these paths.