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interdigitation- I need to layout the following, suggestion?

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k_90

k_90

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interdigitation

hi

I need to layout the following:

a=32
b=16
c=8
d=4
e=2
f=1

I thought of

aaaaaaaabbbbccdaaaaaaaabbbbccde F edccbbbbaaaaaaaadccbbbbaaaaaaaa

any sugestions?
 

interdigitation

If you like this aspect ratio - why not?
However, I'd suggest an 8x8-array (containing 1 dummy), and 36 dummies around (which may be shorter).
 

Re: interdigitation

I'd prefer the 8x8 array but I'm not 100% how best to lay it out!
I also need to slot in another 10 gates somewhere which are not as critical.
 

Re: interdigitation

k_90 said:
I'd prefer the 8x8 array but I'm not 100% how best to lay it out!
Click to expand...
Try a nice mix like that in your suggested linear array. Better mix will achieve less variance, but needs more (symmetrical !) routing effort and area.
k_90 said:
I also need to slot in another 10 gates somewhere which are not as critical.
Click to expand...
You could use the surrounding outside dummies for these!
 

interdigitation

Hi
I think with this way its good(considering routing)
BAAAAABAAAAAB
ABACDACADCABA
BCABE BF BEBACB
ABACDACADCABA
BAAAAABAAAAAB

regards
rajesh
 

interdigitation

Yes, a very good symmetry (2 A dummies included).
Try to keep the symmetry with the routing, too!

Cheers, erikl
 

Re: interdigitation

Guys...Better go for...the first interdigitation pattern...for current mirrors that is enough...one modification is bring the single ds together and make them 2d at one end another at another end..so that you cam eliminate the cuts....!!!Correct me if I am wrong anywhere...!!!
 

Re: interdigitation

varma_cs012 said:
Guys...Better go for...the first interdigitation pattern...for current mirrors that is enough...one modification is bring the single ds together and make them 2d at one end another at another end..so that you cam eliminate the cuts....!!!Correct me if I am wrong anywhere...!!!
Click to expand...

Do you think a linear chain of 63 transistors (with a width of gateLength+S+D contacts) results in a good aspect ratio for low mismatch?
 

Re: interdigitation

I ended up doing....

Z1 = A B A C A G B A D A E B A C A G B A
Z2 = A B A C A G B A D A G B A C A G B A

Then you have (with two rows):

Z1 F Z1
Z2 X Z2

x being a dummy device.

job done :)
 

interdigitation

Good aspect ratio! "G" are your non-critical gates? Then I would have put each 2 of them at the outside, as "dummy replacements". But now don't change!
___
BTW (just a hint) : Before plotting, click Options -> Display... (o) and "Show Text Justification" <off>.
Then even single characters will be legible ;-)

Oh, just saw it: Thanks a lot for your kind donation! And congratulations to your tapeOut!

erikl
 

interdigitation

Yes aspect ration is nice , aproaching a aspect ratio towards square shape ia always good for reducing x,y gradient effects.Also I don't see dummy transistors at the ends, putting dummy transistors at the end is important to take care of etching and also the environment is same for all transistors.

Added after 16 minutes:

Guys,
Do you have this book :
IC Layout Basics : A Practical Guide
by Christopher Saint, Judy Saint

Can you pls send that on my mail
rajeshkr1979(at)rediffmail.com

Thank you very muh
-rajesh
 

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