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mutiple clock domain , method to avoid clock skew

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kiranks9

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lockup latch ocv

There are two clocks in a design, when we are doing scan insertion, adding lockup latches for avoiding the Clock Skews. Is there any other method to avoid clock skew in multiple design other than lockup latch? please let me let know
 

lockup latch with ocv

kiranks9 said:
There are two clocks in a design, when we are doing scan insertion, adding lockup latches for avoiding the Clock Skews. Is there any other method to avoid clock skew in multiple design other than lockup latch? please let me let know
Click to expand...

If you take care of the skew between the two clocks while closing the testmode timning, you may aviod the lockup latch. But I am not sure about the silicon results.
 

Re: mutiple clock domain

yes this is rightly said, balancing both the scan clocks for the required skew limit should help and validating TEST STA for all the modes and corners and OCV(on chip variation) should aid your confidence of the design.

what do you loose having a lockup latch across the clocks ?

myprayers,
chip design made easy
https://www.vlsichipdesign.com
 

Re: mutiple clock domain

in fact ,with the process become smaller and smaller , the clock issue you should consider more with your tool!
 

Re: mutiple clock domain

yah v have another method other than lookup latch is to mention pin as PRESERVE PIN in clock tree specification file so that clock tree algorithm makes best to reduce skew .......

thanku......
 

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