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Assur@ LVS checking problem

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wccheng

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Dear all,

I am using Assur@ to do LVS checking. In my layout view, it consists of 2 dummy transistors. However, 2 dummy transistors do not consist in schematic view. It is so strange that the Assur@ LVS does not report error of this. Does it need to set anything in order to give the error report in this case?

Thanks

wccheng
 

What i think

In LVS basically nodal information of both (layout and schematics ) compared with eachother in any tool.

Now if you have used dummy tansistor in lay out and you have not connected its any part to any net then it will not show error in LVS eventhough in your schematic that transistors are not there.

What i suggest in dummy transistors connect all sources and drain to equat potantiaol and then try.

If any other answer please let me know.
shitansh_vaghela@yahoo.co.in

HTH
 

i have done it .However, the same result. not workable.
 

It can be result of work of 'filter' avCompareRule (for example 'filter MOS -J'). Check compare.rul and Assura LVS GUI settings.
 

Thanks for your helping. The compare.rul set all things are filter. So, it could not check out the dummy problem.

pit1000 said:
It can be result of work of 'filter' avCompareRule (for example 'filter MOS -J'). Check compare.rul and Assura LVS GUI settings.
Click to expand...
 

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