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vhdl - what is the meaning of generic to an vhdl's entity

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Tom2

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vhdl_quenstion

Is anyone who know what is the meaning of generic to an vhdl's entity???
 

Re: vhdl_quenstion

This is a parameter which can alter entity contents at the time of synthesis.

Consider this small code:

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity csa is
	generic (
		N: integer:=32
	);
	port(
		A : in STD_LOGIC_VECTOR(N-1 downto 0);
		B : in STD_LOGIC_VECTOR(N-1 downto 0);
		C : in STD_LOGIC_VECTOR(N-1 downto 0);
				 
		Z : out STD_LOGIC_VECTOR(N-1 downto 0);
		COUT : out STD_LOGIC_VECTOR(N-1 downto 0)
	);
end csa;

architecture behavioral of csa is
begin

	Z<=((not A) and (not B) and C) or ((not A) and B and (not C)) or (A and (not B) and (not C)) or (A and B and C);
	COUT<=(A and B) or (A and C) or (B and C);

end behavioral;

Here the "generic" defines parameter N that can be used to set arbitrary port width.
 

Re: vhdl_quenstion

For the code's example if you don't write as a generic,
has it any impact on the design???
 

Re: vhdl_quenstion

I understand generic in vhdl's entity is the declaration of "constant parameter"


Simply it's constant.
 

vhdl_quenstion

i have just started reading VHDL stuff.
Can any one plz provide a link for those VHDL books which are for the Beginers .
I am a good programer in C++ but VHDL is giving me a tough time. so ineed some material which stars explaining VHDL from very basic level..
 

Re: vhdl_quenstion

i have just started reading VHDL stuff.
Can any one plz provide a link for those VHDL books which are for the Beginers .
I am a good programer in C++ but VHDL is giving me a tough time. so ineed some material which stars explaining VHDL from very basic level..
Click to expand...


Here's good book for VHDL beginer.

http://ifile.it/hl5s1iy

all examples are usable and examples with many source codes.
 

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