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  1. #1
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    How to do a Nanosim fast Spice simulation?

    Hi all,

    I wish to do a nanosim fast spice simulation.

    I am confused about how to do this.
    I have the SPEF file, .mod file, the gate-level verilog netlist and a
    test-bench.

    Is it possible to use the test-bench directly or must I generate
    a .vcd file and then convert the .vcd file to .vec file with the
    vcd2vec command?

    How do i set my power supply voltage etc?

    Please help, I am totally lost!
    N

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  2. #2
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    nanosim know supply voltage

    Quote Originally Posted by caterpede
    Hi all,

    I wish to do a nanosim fast spice simulation.

    I am confused about how to do this.
    I have the SPEF file, .mod file, the gate-level verilog netlist and a
    test-bench.

    Is it possible to use the test-bench directly or must I generate
    a .vcd file and then convert the .vcd file to .vec file with the
    vcd2vec command?

    How do i set my power supply voltage etc?

    Please help, I am totally lost!
    N
    You can directly use the verilog testbench directly. You can define the power suppiles in the config files like

    ************************************
    .global vdd vss vddio vdda vddr vssr
    ************************************
    .param vddrval=1.32
    .param vddaval=1.1
    .param vddioval=1.0
    ************************************
    Vvddio vddio 0 DC vddioval
    Vvdda vdda 0 DC vddaval
    Vvddr vddr 0 DC vddrval
    Vvssr vssr 0 DC 0



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  3. #3
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    nanosim help

    Hi,

    I still can't really figure out how to use the testbench directly. How should I do that? Should I use the verilog libraries?

    regards



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  4. #4
    Full Member level 2
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    nanosim spi

    Quote Originally Posted by caterpede
    Hi,

    I still can't really figure out how to use the testbench directly. How should I do that? Should I use the verilog libraries?

    regards
    there are two scnearions here

    1. if your design is complete spice and tb is verilog use the following way, here i pasted all the spi and other files
    example.spi file:

    * ----------------------------------------------------------------------
    * | include sch & library |
    * ----------------------------------------------------------------------
    ************************************
    .inc '../model_spice/*.sch'
    ************************************

    .inc '../libs/globals.prm'

    .protect
    .lib '../libs/fets.lib' BI
    .lib '../libs/res.lib' L
    .unprotect

    ************************************
    .temp 125
    .option scale = 1.0u
    ************************************
    .global vdd vddio vss vssa vtt vdda vddaux vddiobrd vddpx
    ************************************
    Vvdd vdd 0 DC vddburn
    Vvddio vddio 0 DC vddioburn
    Vvss vss 0 DC 0
    Vvdda vdda 0 DC vddaburn
    Vvssa vssa 0 DC 0
    Vvtt vtt 0 DC vttburn
    Vvddaux vddaux 0 DC vddauxburn
    Vvddiobrd vddiobrd 0 DC vddiobrdburn
    Vvddpx vddpx 0 DC vddburn
    ************************************

    example.init
    --------------
    choose nanosim -nspice ../model_spice/example.spi -nhspf ../model_spice/example.spf -C ../nano_ctrl/example.cfg -o ./sim.scan.bi_temp/nanosim_example;
    set rmap ../nano_ctrl/rmap.map;

    run command:
    -----------------
    bsub vcs -n 2 -q long -I -m lnx64_ib -toolvers Y-2006.06-6 -feat nanosim2006.06 -feat debussy -- -R verilog_testbench.v +ad=../nano_ctrl/example.init +error+100000 -Mdir=./VCS_bin_bi/ -o ./VCS_bin_bi/simv -l ../logs/example.log -full64

    incase if you have any doubt, send me ur mail id i will get back to you.



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