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phase lock loop locking but not at desired frequency

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robismyname

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I managed to get my PLL to lock from frequncy 2410MHz - 2448MHz (see attached-pure sinusoid carrier)

My desired locking frequencies are 2260MHZ-2343MHz. The PLL doesn't lock at these frequencies for some reason (I attached a screenshot that shows how the the frequency response looks at 2300MHz)

My loop filter is second order designed for 1/10th the phase detect frequency
20,000kHz/10 = 2MHz. I attached the loop filter design as well.

My VCO (ROS-2500-2319+) freq range is from 2066MHZ-2646MHZ.
Im using the ADF4252 PLL.

Any ideas on what the problem may be?
 

Did you check your crystal reference frequency? If the crystal is off frequency, the PLL will be off frequency
 

toonafishy said:
Did you check your crystal reference frequency? If the crystal is off frequency, the PLL will be off frequency

my tcxo is 9.999875MHz. Thats 125 Hz off center from 10MHz, do you feel that this is causing my problem?
 

This is not that uncommon. The reason is usually one of the following:

1) the PLL chip does not support the exact divisor ratio that you pick. Even though it the data sheet might tout "divides from 100 to 20,000", there are often non-allowed divisors, such as 167-178, 1902-1988,....
The manufacturer often provides programming software for the chip that runs on a PC computer. Try programming in your exact reference frequency, VCO frequency, and PD comparison frequency, and it will tell you if it is valid or not.

2) Maybe it is not really phase locked? Try moving the reference frequency, say 10 KHz, and see if the VCO frequency really jumps 10 KHz X divisor ratio.

3) Check the VCO tuning voltage at 2410 MHz. What is it? To phase lock any lower you would need to go lower in tuning voltage than that. Can you? In other words, are you locked at 0.1 Volts, and to tune any lower you would have to go negative, but you can not since the VCO varactor would forward bias, or some other limiting phenomenon. Your loop filter is purely passive, so you are going to be limited to how much tuning voltage you can generate. Maybe you need to add an op amp to get a bigger tuning voltage range (or a VCO that better falls into the frequency range you need).

4) and of course, the ever present misprogrammed bit problem. Maybe you are just sending it the wrong bits! Once again, the manufacturers PC control program is your friend. Program in your frequencies, and look at what bits the PC control program is sending to the chip. Is this the same bit pattern you expected?
 

This is very simple. You have selected incorrect PFD frequency. Based on your loop filter design, your PFD is 2 MHz. You cannot achieve such frequency as 2343 MHz, because you do not get an integer as a result if you divide the desired output freq (2343MHz) by 2. So you must change your PFD frequency to e.g. 1 MHz.

Ny the way, your TCXO measurement look really bad... the level is -93dBm? I would expect at least some 0...+5dBm power level for TCXO output (if the output is LVCMOS or similar) Whats wrong with that.

And I would not expect any exact 2448 MHz absolut frequency since our reference is not exactly 10 MHz. You coulf replace your TCXO with a signal generator which is synchronized to same reference with the spectrum analyzer. Moreover, you have selected too wide span in your spectrum analyzer in order to measure center frequency with a simple marker. Select about 10kHz span and then measure the center frequency with the marker. Of course the resolution bandwidth of the spectrum analyzer must be adjusted accordingly.
 

What looks unusual to me is the loop filter schematic.
You have soldered 1st and 3rd pole, that is really unusual. Did you check loop stability in ADI software? The phase margin should be larger than 45-50 deg.

I hope it can help.

Mazz
 

HI,
Have you worked on ADF4110 PLL?

Thanx,
Viswanath.
 

There are many possible reasons for the pll not to lock. I have written about several solutions to different problems **broken link removed** and I intend to add more.
 

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